From Concept to QoR: Practical Generative AI for ASIC Managers and Engineers
December 12 @ 9:00 am - 10:00 am PST
Be among the first to see how Generative AI is advancing hardware design workflows, providing solutions that reduce complexity and enable better results without steep learning curves. Witness how these tools offer immediate, practical benefits for real-world use cases.
What You’ll Learn:
This session offers a unique opportunity to explore how Generative AI solutions with Rise Design Automation are reshaping hardware design and verification workflows. Attendees will learn advanced techniques for enhancing design quality, accelerating IP and module development, and making more informed design trade-offs with minimal learning curves. Designed for engineers and managers with a background in hardware design, this session is ideal for those eager to adopt innovative methods and witness how these tools perform in practical scenarios.
Key Takeaways:
Generative AI and Accelerated IP Development
- Understand the value of adopting a shift-left approach to enhance design abstraction and streamline processes beyond traditional RTL methods.
- Learn how project timelines can be reduced, enabling faster IP/module development and delivering improved Quality of Results (QoR).
Design Generation
- Explore how AI automates the creation of RTL code from natural or high-level languages, such as SystemVerilog, SystemC, and C++.
- Discover tools for AI-powered code completion, generation, and refactoring that ensure maintainable, high-quality code with less manual effort and help RTL designers achieve excellent QoR without deep HLS expertise.
Integrated Design Optimization
- Early Design Exploration: Understand intelligent and iterative refinement techniques that help minimize late-stage design surprises.
- Gradual Refinement: Explore workflows that support continuous refinement of high-level designs, incorporating backend metrics and physical insights as they progress.
- Critical Parameter Optimization: Learn about AI-powered Design Space Exploration (DSE) to evaluate and optimize configurations such as loop unrolling, pipelining, and memory synthesis for superior Power, Performance, and Area (PPA).
- Integrated EDA flows: Discover how Rise’s Generative AI integrates with both Synopsys and Cadence RTL Verilog workflows, bridging early design exploration with downstream verification and physical implementation.
Real-World Applications
- Hardware Design: Learn how Gen AI allows designers to focus on architectural innovations rather than manual coding.
- Verification Processes: Examine ways for AI to automate early verification steps to detect issues earlier, with metrics and reduce the rework in later stages.
- Collaborative Approaches: See how AI-driven tools enhance collaboration among system architects, hardware designers, and verification engineers, creating more cohesive and efficient workflows.
Flexible Deployment Options
- Deployment Support: Understand compatibility with cloud platforms like Amazon Bedrock and Microsoft Azure, as well as options for on-premises environments that can be tailored to different operational and organizational needs.
- Legal Considerations: Review best practices for addressing data privacy, intellectual property concerns, and compliance with regulatory frameworks when leveraging AI-driven methodologies.
Who Should Attend:
- Design Engineers: Discover AI-guided strategies to improve control paths, data flow, and overall performance.
- Verification Engineers: Learn techniques to integrate early verification processes, reducing risks and enhancing efficiency.
- Project Leads: Gain insights into managing trade-offs in power, performance, and area while introducing innovative AI tools into existing workflows.
- System Architects: Explore approaches for early modeling and validation of architectural decisions, optimizing outcomes and preventing late-stage challenges.
- Design Managers/Methodology team: Understand how AI combined with raising design abstraction can dramatically improve the overall productivity, quality and ability for your design teams to deliver on new projects
Speakers
Mike Fingeroff, Chief of High-Level Synthesis (HLS) With over 20 years of experience in hardware design automation, Mike has specialized in High-Level Synthesis (HLS), focusing on machine learning and early performance modeling using SystemVerilog, SystemC, and MatchLib. He is the author of The High-Level Synthesis Blue Book, and his expertise includes C++, SystemC, and video and wireless algorithms.
Allan Klinck, Co-Founder Allan is a co-founder of RDA and a technology leader with expertise in high-level design and AI/ML frameworks for verification. He has driven innovation in verification and low-power technologies, helping teams enhance efficiency and performance in modern, complex designs.
Ellie Burns currently serves as the Head of Marketing at Rise Design Automation (RDA). With over 30 years of experience in the semiconductor and EDA industries, she has held diverse roles in engineering, applications engineering, technical marketing, product management, and senior leadership, specializing in driving business growth through strategic marketing.