CadenceTECHTALK: Driving Intelligent System Design with 3D-IC Multiphysics

As the industry reaches the limits of device scaling at advanced nodes, there is a growing demand for increased computing performance and data transfer in hyperscale data centers and AI designs. Advanced systems-on-chip (SoCs) are approaching the maximum size limits, and there is a need to find innovative solutions to continue scaling according to Moore’s law and achieve better performance with lower power consumption. Stacking chips in the same package (3D) and using a multi-chiplet system with silicon interposers on the same package (2.5D) are emerging as preferred solutions, but they come with their own challenges.

This webinar will discuss the requirements, challenges, and solutions for 3D-IC design and analysis achieved through an integrated 3D-IC platform. By receiving early feedback from system-level analysis processes, 3D-IC designers can benefit from a system-driven approach to power, performance, and area (PPA) and avoid overdesigning individual chipsets.

You will learn about:

• The requirements, challenges, and solutions for 3D-IC design
• How the analysis of 3D-ICs is done through an integrated 3D-IC design platform
• How feedback from early system-level analysis provides a system-driven approach to PPA