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Improving Initial RTL Quality

September 15, 2021 @ 8:00 am - 9:00 am PDT

SIemens EDA, September 15
Development projects, whether FPGA or ASIC SoCs or IP, run into late surprises that quickly result in schedule slips, expensive rework, and/or difficult feature cuts. It is possible to find entire classes of issues without waiting for a testbench. This webinar will introduce you to a testbench-free designer-driven verification flow, resulting in a lower cost and deterministic development so you can avoid surprises like working later nights and scuttled holidays.
This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
What You Will Learn:
  • What the impact of non-optimal RTL quality is to your development
  • Why providing the highest quality RTL improves overall team performance
  • How to accomplish an improved RTL quality-focused flow

Who Should Attend:

  • Design & Verification Engineers & Managers


September 15, 2021
8:00 am - 9:00 am PDT
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Siemens EDA
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