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Latch-Up 2024: Boston
April 19 @ 8:00 am - April 21 @ 5:00 pm PDT
You are all invited!
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston, MA, USA.
Latch-Up is a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf.
So save the date, register to attend, and submit a presentation or proposal if you have a project or idea on the topic to share!
Questions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org.
Submit a talk
We encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available.
So if you’ve designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we’d love to have you join us to share your experience.
Presentations are submitted through the registration process and we will let you know if your presentation was accepted.
Tickets and registration
Attendance of Latch-Up is free of charge. To help us organizing the event, you are required to register on Eventbrite. Please register as soon as possible, as we have to close registrations as soon as the room capacity is reached.
Attendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat.
We ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event.
Friday
| When | What |
|---|---|
| 9:00 | Welcome |
| 9:20 | Caster: An Open-source E-Ink Controller |
| 9:40 | Teaching Modern EDA using a Tapeout-Centric University Course |
| 10:00 | Break |
| 10:20 | CedarEDA for open source silicon |
| 10:40 | Cohort: Software-Oriented Acceleration for You, Me, and Our Heterogeneous SoCs |
| 11:00 | Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture |
| 11:20 | Lunch |
| 12:20 | Towards Cycle-accurate Simulation of xBGAS |
| 12:40 | Artifact Evaluation for the Field Programmable Gate Array Community |
| 13:00 | Chisel 6 and beyond |
| 13:20 | MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL |
| 13:40 | Break |
| 14:40 | Riding The Wave: Building Wave Pipelines in FPGAs |
| 15:00 | Giving Students A Byte of Open-Source: Advancing Hardware Education |
| 15:20 | Break |
| 15:40 | Open-source resources for learning the Bluespec HL-HDLs |
| 16:00 | PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface |
| 16:20 | Transition to Draper |
| 17:00 | Talks(30-40m) at Draper |
| 18:00 | Transition to lightning Talks |
| 19:00 | Lightning Talks |
| 20:00 | Go home |
Saturday
| When | What |
|---|---|
| 8:40 | Welcome |
| 9:00 | Open source RTL verification with Verilator |
| 9:20 | Sonata: A development platform to enable exploring the use of CHERI for embedded applications |
| 9:40 | Transparent Checkpointing for Fault Tolerance in RISC-V |
| 10:00 | Break |
| 10:20 | HDLAgent, Enhancing Hardware Language in the age of LLMs |
| 10:40 | Spade: An HDL Inspired By Modern Software Languages |
| 11:00 | Switchboard: Calling All Hardware Models |
| 11:20 | Lunch |
| 12:20 | From an Open-Source ISA to Open-Source HW to Open-Source Silicon |
| 12:40 | Open Source Hardware: Hacking Silicon for Fun (instead of profit) |
| 13:00 | A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation |
| 13:20 | UMI: Universal Memory Interface |
| 13:40 | Break |
| 14:20 | ABC: The Way It Should Have Been Designed |
| 14:40 | BYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development |
| 15:00 | Beyond EDA lies Edalize |
| 15:20 | Break |
| 15:40 | RF Front-end receiver design for 2.4GH/5GHz WiFi application |
| 16:00 | CACE Study: Open source analog and mixed-signal design flow |
| 16:20 | IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead |
| 16:40 | Tiny Tapeout: custom silicon open to all |
| 17:20 | Meet at Flattops |
Sunday
Coming soon