Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs

The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static design verification is an essential part of a robust verification process that includes advanced linting and Clock Domain Crossing (CDC) analysis.

In this webinar, we will provide a methodology overview of advanced linting and CDC analysis, demystify the type of design problems they solve and show how they can be added to the Microchip Libero® tool flow. We will then show a working example of how these methods can be applied to Microchip PolarFire® SoC FPGA Icicle designs. Starting from Libero IDE, we will show automated project conversion into the Aldec ALINT-PRO environment for advanced linting, block and top-level constraints development and CDC analysis.

Presenter BIO
Alexander is Aldec’s ALINT-PRO Product Manager. He has accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates projects in companies such as IBM, Nortel, Ericsson and Synopsys Inc. He has combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.