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Low-Power Verification Using Xcelium Simulation
January 25 @ 9:00 am - 10:00 am PST
Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.
The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. This webinar will focus on the functional verification of the RTL with the power intent defined in the IEEE 1801, aka UPF, format.
Low-power verification adds another layer of complexity to functional verification. Power-related issues often appear late in the verification cycle, can be difficult to fix, and may impact project schedules.
Low-power verification using Xcelium simulation enables design verification teams to catch low-power issues very early in the verification cycle at the RTL phase with best-in-class performance and providing complete low-power coverage.
Find out how
- The Xcelium platform can automate low-power checkers and assertions using UPF Information Model, query commands, and custom built-in functions
- Xcelium simulation has advanced technology to differentiate the source of “X” coming from LP versus functional “X”
- Mixed-signal designs with real power supplies and custom resolution functions work seamlessly with UPF
- The Verisium Debug App’s advanced capabilities work to debug the complex low-power simulation
- To implement best practices using Xcelium Simulation and other new capabilities