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Mixed-Signal SoC Verification Simplified with Xcelium Simulator

February 17, 2022 @ 3:30 pm - 5:00 pm IST

Cadence, February 17, 2022

Analog and mixed-signal verification has always been a challenge for design and verification engineers. It has become tedious with the increasing complexity of SoC designs. Because the analog behavior of key design blocks cannot be simulated effectively using traditional verification methodologies, new methodologies and solutions like real number modeling (RNM) for analog functional blocks are getting rapid traction.

Cadence has long been a leader in analog and mixed-signal verification. The Cadence® Xcelium™ Logic Simulator provides easy integration of analog and digital blocks, high-performance RNM, and easy and fast debug for mixed-signal verification. It is important that an RNM solution eases the replacement of the real number model with an equivalent block implementation (SPICE or Verilog AMS), which allows verification with different levels of abstraction.

Join this webinar to learn how Cadence is providing effective verification and debug methodologies using RNM of analog blocks for mixed-signal SoC verification.


Thursday, February 17, 2022


10:00 GMT / 11:00 CET / 12:00 EET and Israel / 15:30 IST


February 17, 2022
3:30 pm - 5:00 pm IST
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