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Optimizing Simulations for Efficient Coverage Collection
October 20 @ 11:00 am - 12:00 pm PDT
Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis of coverage on your designs might look challenging but with a few steps you can optimize your design flow to make the process much simpler. Many times, simulations are not run with coverage because of the long simulation run times, but if you efficiently plan your simulations and scripting, collecting coverage and analyzing the results will be a lot easier.
- Introduction to Coverage
- Code Coverage
- Functional Coverage
- Automation using scripts
- Live Demo
- 45 min presentation/live demo
- 15 min Q&A
Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions that include Digital Design Engineer Verification Engineer and Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.