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Practical Flows for Continuous Integration: Making The Most of Your EDA Tools

November 16 @ 8:00 am - 9:00 am PST

Siemens EDA, November 16

Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.

In this webinar we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.

What You Will Learn:

  • Guidelines for deploying formal apps to effectively root cause design bugs
  • How to build and customize tool flows for continuous integration
  • Recommendations for introducing continuous integration

Who Should Attend:

  • Design & Verification engineers and Managers from medium to large size teams who are interested in maintaining a stable, functioning code base during active development
  • Especially applicable for teams who rely exclusively on simulation for functional verification

Products Covered:

Neil Johnson
Questa Simulation Product Engineer
Siemens EDA

Neil Johnson is a long time verification engineer with a history in product development as both a full-timer and a consultant, now working with Siemens EDA as a product engineer focused on SystemVerilog language support and performance within QuestaSim.

Chris Giles
Design Solutions Product Manager
Siemens EDA

Chris is a member of the DVT Product Marketing team, managing the Design Solutions product line, including the CDC+RDC product lines as well as the HDL Designer Series. Chris comes to Siemens EDA from the user community, with decades of experience in IP and ASIC/SoC/FPGA R&D and management, with products deployed in consumer, military, compute and storage markets and at companies such as Hewlett Packard Enterprise, Honeywell, Seagate, Micron, NEC and LSI Logic. The author of 18 patents in areas such as hardware virtualization, security, processor architecture, synchronization schemes, and hardware prototyping, Chris received an MSEE from Stanford University in California and a BSEE from Rice University in Texas.

Joe Hupcey III
Questa Formal Product Manager
Siemens EDA

Joe Hupcey III is a part of the Siemen EDA’s Product Management team for Design & Verification Technologies; based in Siemens EDA’s office in Silicon Valley, CA. He is responsible for the Questa Formal product line of automated applications and advanced property checking. Prior to joining Mentor, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.

Details

Date:
November 16
Time:
8:00 am - 9:00 am PST
Event Categories:
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Event Website

Organizer

Siemens EDA
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