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Solution for 3D-IC Interposer Signal Integrity
July 26 @ 10:00 am - 11:00 am PDT
3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design data being accurately modeled with 3D FEM extraction. The Cadence Clarity 3D Solver has the unique ability to efficiently import and solve for complex structures, including degassing holes. Accurate interconnect models can then be cascaded with IBIS I/O models for end-to-end signal integrity analysis and confirm that high-speed signals meet compliance testing.
Included will be a step-by-step approach to importing GDS into the simulation environment. The interposer multiblock analysis workflow in Clarity 3D Solver will show how to edit the layout, simulate, and then view all simulation results.
If you think performing channel extractions on a large interposer is a complex and time-consuming process, this is the perfect webinar for you.