Skip to content
Loading Events

« All Events

  • This event has passed.

The Power of Verilog’s PLI and VPI for FPGA Designs

April 13, 2023 @ 11:00 am - 12:00 pm PDT

Aldec, April 13, 2023

A logic simulator’s programming interfaces can be used for not only verifying logic IP but also the co-development of logic and embedded software.

Our ‘Introducing Logic Simulator Programming Interfaces for FPGA designs’ three-part webinar series starts on April 13.

Our guest presenter for this series is Simon Southwell, from Anita Simulators, and the schedule is as follows:

Part 1: The Power of Verilog’s PLI and VPI – April 13.
Part 2: The Power of VHDL’s VHPI – April 27.
Part 3: The Power of SystemVerilog’s DPI – May 11.

All three webinars will be live and held twice – at 15:00 CEST and 11:00 PDT. Each will include a Q&A session.

The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development.


The Programming Language Interface (PLI/VPI) is part of the IEEE Standard for SystemVerilog Language Reference Manual. In this part 1 of the webinar series, we will introduce the Verilog PLI and VPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with memory models and virtual processors, sufficient to allow engineers to start creating their own solutions. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available, and well supported, in the Aldec simulation tools.



  • Introduction
  • Verilog PLI
  • Sparse memory model example
  • Verilog VPI
  • Reworked memory model
  • Virtual Processor
  • Demo of Virtual Processor and memory model
  • Conclusions
  • Q&A


Webinar Duration:

  • 45 min presentation/live demo
  • 15 min Q&A

Presenter BIO

Simon Southwell has 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now spending time contributing IP to the open-source community, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project, a verification methodology and VHDL library, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems, system modeling in software, the software/hardware interface and co-simulation of logic and software.

Amongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA, logic verification, HPC (supercomputers), processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modeling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4) and more. Joint or sole author on several logic IP related patents.


April 13, 2023
11:00 am - 12:00 pm PDT
Event Categories:
Event Tags:
, ,
Event Website


View Organizer Website

Leave a Reply

Your email address will not be published. Required fields are marked *