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Understanding Random Stability in SystemVerilog and UVM
November 3 @ 10:00 am - 11:00 am PDT
A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability.
In this webinar, we explain:
- Random stability in SystemVerilog and in UVM, the Universal Verification Methodology
- The pitfalls of poor random number generation and seeding
- How to ensure that simulation results are reproducible in native SystemVerilog and in UVM through a careful presentation of hierarchical seeding, manual seeding, thread stability, and object stability
- Exactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation.
Examples written in the IEEE Std 1800™ SystemVerilog language and UVM 1.2 will be shown running on the Questa Advanced Simulator from Siemens.
This training webinar is presented by Doulos Senior Member Technical Staff, Matthew Taylor and will consist of a one-hour broadcast with interactive Q&A available to attendees throughout. Attendance is free of charge.
Matthew Taylor , Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.