- This event has passed.
Verisium Debug for UPF Low Power Design
June 27 @ 11:00 am - 12:00 pm PDT
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs.
What you will learn
- Understand features available in Verisium Debug
- Learn about the low-power debug capabilities available in Verisium Debug
- Learn how to debug UPF low-power designs with Verisium Debug
Who should attend
- Design engineers
- Verification engineers
- CAD engineers