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Verisium Debug for UVM Testbench
October 4 @ 11:00 am - 12:00 pm PDT
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench.
What you will learn
- Understand the features available in Verisium Debug
- Learn about the UVM debug capabilities in Verisium Debug
- Learn to debug UVM testbench using Verisium Debug
Who should attend
- Design engineers
- Verification engineers
- CAD engineers