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Why Chiplets with UCIe are the Next Big Thing
November 14 @ 11:00 am - 12:00 pm PST
Artificial intelligence (AI) and virtual reality (VR) require fast, efficient, low-power technologies. Transistors are becoming harder and harder to shrink, so chiplets are a promising alternative. Chiplets are small, modular dies that use UCIe, an open industry standard, to communicate with each other. Combined in a Systems-on-Package (SoP), they provide superior performance, reduced power consumption, and increased design flexibility for customized applications such as cell phones, autonomous vehicles, etc. In this panel session, signal and power integrity experts will discuss:
- Industry trends and why chiplets with UCIe are the next big thing.
- Signal and power integrity considerations when integrating chiplets and UCIe interfaces.
- EDA tools evolved, and how to streamline chiplets integration into the design workflow.
HeeSoo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division, located in Santa Rosa, Calif. He has held several positions in Keysight Technologies, Agilent Technologies and Hewlett-Packard, including consulting business manager, technical marketing lead and field applications engineer since 1989. Prior to these positions, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF, microwave and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University, South Korea.
Heidi Barnes is a Senior Application Engineer and Power Integrity Product Owner at Keysight, specializing in High-Speed Digital applications. With 26+ years of experience in the field of electronic design automation, her recent activities include the application of electromagnetic, transient, and channel simulators to solve signal and power integrity challenges. She contributed to the IEEE-370 Standard on fixture removal for high-frequency interconnects and is Co-Chair for the IEEE EPS EDMS Packaging Benchmark Sub-Committee. Heidi holds five patents and was awarded the DesignCon Engineer of the Year in 2017.
Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques, including de-embedding algorithms, measurement/model correlation, high-speed measurements for real-time & sampling oscilloscopes, and BERTs & AWGs. He has participated on many standards committees, including PCI-SIG, USB-IF, SATA-IO, and JEDEC, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.