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Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim

April 16 @ 8:00 am - 9:00 am PDT

Siemens, April 16, 2024

Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process.

Learn how the latest innovations in QuestaSim address these challenges by enabling full off-line debugging freeing up simulation licenses for more simulations runs per day. Also, learn how unique debugging features like driver tracing, biometric search, temporal causality trace back, and much more will enable you root cause bugs more straight forward and faster. All the while delivering industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC.

What you will learn:

In this Web Seminar, we will highlight the key innovations in QuestaSim that enable full debug visibility with significant reduction in simulation performance overhead and waveform database size. For existing QuestaSim users, we will show the simple change to scripts to see a 2X performance boost and 3X reduction in waveform database.

We will highlight the debug features in our Visualizer debugger now included as part of every QuestaSim license, such as:

  • Driver/receiver tracing from wave and source code
  • ‘x’ tracing through sequential logic and time
  • FSM debug & cross probing
  • Schematics exploration with smart hierarchical flattening and pruning.
  • Waveforms with cross probing & biometric search
  • Design search by type

We will step through some design and testbench examples showing how these features can speed up root causing bugs and tackle complex logic that may be impossible for humans to figure out.

Who should attend:

Ultra Low Latency FPGA Designers in the High Frequency Trade industry

What/Which Products are Covered:  

  • QuestaSim with Visualizer Debugger
Rich Edelman
Product Engineer, Siemens EDA

Rich Edelman is a Product Engineer at Siemens EDA and is responsible for the Visualizer Debug Environment. He holds a Bachelor of Science Degree in Electrical Engineering, a Bachelor of Science Degree in Computer Science, and a Master of Science Degree in Computer Science from Washington University in St. Louis. Prior to Siemens EDA, Rich worked for a C Synthesis company, a compute farm company, Design Acceleration, and a couple of ASIC houses. Rich’s best days are in Yosemite backpacking – or at least dreaming about it.


April 16
8:00 am - 9:00 am PDT
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