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Workshop on the Evolution of SystemC Standards

September 15, 2022 @ 4:00 pm - 6:00 pm CEST

Accellera, September 15, 2022

The SystemC Evolution Fika is a series of online workshops to discuss the latest SystemC developments and applications. We refer to these workshops as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about.

Event information

Date: 15 September 2022
Time: 16:00 – 18:00 CEST
Location: Online, Virtual Workshop.


Registration is free of charge. Register here.

NOTE: After registration you will receive an email including meeting details to attend the online event.

Organization Team

  • Ola Dahl, Ericsson (Chair)
  • Martin Barnasconi, NXP
  • Jerome Cornet, STMicroelectronics
  • Christian Sauer, Cadence
  • Mark Burton, Qualcomm
  • Peter de Jager, Intel


A fault-injection methodology for the system-level reliability analysis of computing systems modeled in SystemC

Presenter: Antonio Miele, Ph.D., Politecnico di Milano, Italy

Fault injection is the commonly-used strategy for evaluating the reliability of a mission-/safety-critical computing system in the various phases of the design flow. Depending on the specific phase of the design flow fault injection is employed, it is required to define 1) fault models, describing the effects of physical faults in the specification/implementation of the computing system, 2) fault injection techniques actually corrupting the specification/implementation of the computing system to simulate/emulate the fault occurrence, and 3) error analysis strategies to study the effects of faults on the main outputs and within the system. This talk provides an overview of our past experiences in defining a fault injection and analysis framework integrated in a SystemC virtual simulation platform for multicore computing systems.

A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures

Authors: Peer Adelt, Bastian Koppelmann, Wolfgang Mueller, Christoph Scheytt

Presenter: Peer Adelt, Heinz Nixdorf Institut/Universität Paderborn, Paderborn, Germany

Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.

More information

Dynamic Fault Injection with SystemC AMS for Quantitative Safety Verification

Presenter: Thomas Markwirth, Fraunhofer IIS/EAS, Dresden, Germany

In this presentation we demonstrate how SystemC AMS can be used for quantitative safety verification of a Battery Management System (BMS). We start out by presenting our technology for dynamically introducing fault structures into SystemC AMS models at runtime. The injection is done at the beginning of the simulation by dynamically rewiring the involved netlists. During the simulation, faults can be activated or deactivated triggered by sequences or statistically. We then show how this feature can be applied in quantitative safety verification, e.g. to determine the diagnostic coverage (DC) of a safety mechanism.

More information:


September 15, 2022
4:00 pm - 6:00 pm CEST
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Accellera Systems Iniative
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