EDA
FPGA Frontrunner Meet & Greet
Thales 350 Longwater Avenue, Reading, United KingdomThe FPGA Front Runners event will be hosted by Thales at their venue in Reading. The event will focus on “Security at System Level, and what security features we need in our FPGA to support this”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What is Security in FPGA-based… Read More »FPGA Frontrunner Meet & Greet
Silvaco UseRs Global Event (SURGE) 2023 – Japan
Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Read More »Silvaco UseRs Global Event (SURGE) 2023 – Japan
Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding design-for-test (DFT) logic required for manufacturing tests has also become more complex. Increasing transistor density, combined with a growing mix of… Read More »Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation
Auto-generation of Verification Infrastructure for IP to SoC
Agenda (BST): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT Agnisys 12.30 GMT Imperas 12.45 GMT Breker 13.00 GMT Close About DVClub The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe… Read More »Auto-generation of Verification Infrastructure for IP to SoC
Innovative Designs Enabled by Ansys Solutions – IDEAS 2023
ANSYS’ VIRTUAL USER CONFERENCE FOR ELECTRONICS, SEMICONDUCTORS AND PHOTONICS DESIGNERS Join us for the IDEAS Digital Forum — a place to catch up on industry best practices and the latest semiconductor, electronic, and photonic design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights by expert chip designers from… Read More »Innovative Designs Enabled by Ansys Solutions – IDEAS 2023
Latest Innovations and Updates in ASICs with Efabless
In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: OpenFrame - a new version of Caravel that gives 50% more area GPIO configuration questions The new cocotb testing framework IPM - The… Read More »Latest Innovations and Updates in ASICs with Efabless
IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS)
Hilton Maslak Büyükdere Cd. No:233, Istanbul, TurkeyThe IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS) will be held in Istanbul, Turkey 4-7 December 2023. As the flagship conference of IEEE Circuits and Systems Society in Region 8 (Europe, Middle East, and Africa), ICECS 2023 will consist of tutorials, plenary lectures, regular, special and poster sessions focusing on recent trends,… Read More »IEEE 30th International Conference on Electronics, Circuits and Systems (ICECS)
IP-SoC Conference 23 – Grenoble
Hotel Europole 29 rue Pierre-Sémard, Grenoble, FranceA worldwide connected Event !! IP-SoC 2023 will be the 26th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and… Read More »IP-SoC Conference 23 – Grenoble
Conformal User Group Conference 2023 and Technology Day
Cadence Design Systems, Bldg 10 2655 Seeley Avenue, San Jose, CA, United StatesIt’s time for our inaugural CadenceCONNECT: Conformal® User Group Conference and Technology Day held on December 5th at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers to share the latest design and verification practices based on Cadence’s Conformal family of solutions including logical equivalence checking (LEC), low power… Read More »Conformal User Group Conference 2023 and Technology Day
Rigid Flex PCB In-Design Electromagnetic Analysis Workflow
Today's electronic products increasingly use Rigid-Flex PCBs to compress form factors, reduce weight, and increase cost-effectiveness. For many commercially available 3D numerical solver technologies (FEM and FDTD), the electromagnetic (EM) analysis of rigid-flex PCBs has always been challenging due to the complexity of the 3D designs. Much of this complexity comes from bending the board into… Read More »Rigid Flex PCB In-Design Electromagnetic Analysis Workflow
Multi-Die System Verification with Siemens Avery UCIe VIP
Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging Moore’s law, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome… Read More »Multi-Die System Verification with Siemens Avery UCIe VIP
Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include: - Speed and power requirements lead to designs with multiple asynchronous clock domains on different I/O interfaces and data being transferred from one… Read More »Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques