Multi-Die System Verification with Siemens Avery UCIe VIP
December 7 @ 8:00 am - 9:00 am PST
Conventional monolithic SoCs are becoming a bottleneck for power, performance, and area (PPA), creating limitations for Data-intensive applications like high-performance computing (HPC), machine learning (ML) and artificial intelligence (AI), and for hyperscale data centers. These bottlenecks are challenging Moore’s law, hindering the industry’s ability to continue scaling designs. Chiplets are rapidly becoming the means to overcome the slowing of Moore’s Law, but the semiconductor industry needs standardized interconnects to allow scaling up these systems, with 2D, 2.5D and even 3D packaging technologies.
Universal Chiplet Interconnect express (UCIe) is a chiplet interconnect standard that enables seamless interoperation and connectivity between the chiplets/dies without impacting the overall performance. UCIe offers several benefits with lower power consumption, improved performance with the same latency of the system.
In this online seminar, we will introduce you to Siemens EDA’s Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.
What You Will Learn:
- What is the Universal Chiplet Interconnect Express (UCIe)
- Why do we need UCIe in chiplet designs: its evolution and application.
- Design and Verification considerations when planning a UCIe based design.
- Siemens Avery UCIe Verification IP’s unique features.
Environment / Testbench Creation
- Technical Demonstration
Who Should Attend:
- Design, Verification Engineers, Managers and Architects working on or planning UCIe design projects
What/Which Products are Covered:
Luis E. Rodriguez has worked on SoC and IP functional verification for over 17 years including developing and deploying PCIe, CXL, NVMe, and UCIe Verification IPs. He has participated and contributed to several protocol workgroups like PCIe, CCIX, GENZ (Compliance Workgroup chair); and CXL, where he helped define Compliance Testing for CXL 2.0. At Siemens he is focused on the architecture of the UCIe Verification IP, as well as participating in several cross functional teams focused on finding synergies between verification IP and other Siemens EDA tools. He received his Master’s in Computer Science from National Taiwan University and is a fan of learning new languages.
Technical Product Manager
Justin Bunnell is a Technical Product Manager at Siemens EDA, responsible for the architecture and development of Siemens Avery UCIe Verification IP solution along with several other custom VIPs. He has over 12 years of experience in hardware design verification and simulation software development and holds a Master of Engineering Degree in Computer Engineering from Iowa State University.