EDA
Verification Futures Conference 2024 UK
The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures… Read More »Verification Futures Conference 2024 UK
Design, Manage, and Share Data with OrCAD X Cloud Workspaces
The OrCAD X platform allows you to manage and collaborate throughout the PCB design process. The cloud workspaces are available out-of-the-box without any additional setup of internal/external server dependencies. If… Read More »Design, Manage, and Share Data with OrCAD X Cloud Workspaces
VC Formal Virtual Workshop – North America & Europe
Location: Virtual workshop with hands-on labs. This workshop is best suited for attendees based in North America and Western Europe. For attendees based in Eastern Europe or Asia, please register for this workshop being… Read More »VC Formal Virtual Workshop – North America & Europe
DAC 2024
Moscone West San Francisco, CA, United StatesThe premier event for the design and design automation of electronic chips to systems. Autonomous Systems Electronics content in modern autonomous systems (e.g., automotive, robotics, drones, etc.) is growing at an increasingly… Read More »DAC 2024
RISC-V Summit Europe 2024
MOC Conference Lilienthalallee 40, Munich, GermanyThe RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation… Read More »RISC-V Summit Europe 2024
Developing Silicon Carbide DMOSFETS: A Digital Twin Reference Flow
This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco's TCAD platform. Adhering to industry… Read More »Developing Silicon Carbide DMOSFETS: A Digital Twin Reference Flow
Developing Silicon Carbide DMOSFETS: A Digital Twin Design Reference Flow
This webinar presents a comprehensive methodology for the design and optimization of a 1200V Silicon Carbide (SiC) Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (DMOS FET) utilizing Silvaco's TCAD platform. Adhering to industry… Read More »Developing Silicon Carbide DMOSFETS: A Digital Twin Design Reference Flow
FPGA Conference Europe
NH München Ost Conference Center Einsteinring 20, Munich, Aschheim, GermanyThe FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is Europe's leading specialist conference for programmable logic devices. The conference focusses on user-oriented, practically applicable solutions… Read More »FPGA Conference Europe
How to Reduce Thousands of False Errors in 15 Minutes
Analyzing electrical errors across an IP or a SoC at top level, can be a painful and long process, often requiring extensive setup time and hundred of hours to distinguish… Read More »How to Reduce Thousands of False Errors in 15 Minutes
Ensuring my Design Verification is ISO26262 Compliant
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaWith the widespread of the modern automobiles, run and regulated by automotive ECUs, the need for advanced safety features has also become inevitable. And this is why today modern vehicles… Read More »Ensuring my Design Verification is ISO26262 Compliant
Maximize Productivity with Deep Insights into PPA Trajectories
The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data… Read More »Maximize Productivity with Deep Insights into PPA Trajectories
Efficient Way to UVM Constraint Randomization Debug
Become skilled at the art of UVM randomization debugging! Date: Wednesday, July 17, 2024 Time: 10:00am PDT | 1:00pm EDT This webinar equips you with effective strategies to tackle randomization-related errors within… Read More »Efficient Way to UVM Constraint Randomization Debug