EDA
Calendar of Events
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DFT for chiplets & 3D ICs using Tessent Multi-die
DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1,… Read More »DFT for chiplets & 3D ICs using Tessent Multi-die
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3 events,
TSMC 2024 Technology Workshop – Austin
TSMC 2024 Technology Workshop – Austin
08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… Read More »TSMC 2024 Technology Workshop – Austin
Smart methods for DFT chip architecture & validation
Smart methods for DFT chip architecture & validation
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. The… Read More »Smart methods for DFT chip architecture & validation
Keysight EDA Connect Tour – Austin
Keysight EDA Connect Tour – Austin
Keysight is excited to announce the next destination stops of our EDA Connect World Tour: Austin, TX and Burlington, MA. Save the dates for our upcoming events in Austin, TX on May 2 or Burlington, MA on May 16, where we'll explore the future of AI in 6G to 3D Module integration. These technical sessions promise to recharge your… Read More »Keysight EDA Connect Tour – Austin
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2 events,
ChipEx 2024
ChipEx2024, the largest annual event of the Israeli semiconductor industry, will be held on May 7-8, 2024 in Tel Aviv, Israel. ChipEx2024 showcases companies including manufacturers, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world's leading experts address the industry's most relevant issues. The event is… Read More »ChipEx 2024
User2User Europe 2024
User2User Europe 2024
User2User is the perfect opportunity to learn, share and network with fellow technical experts who design leading-edge products using Siemens EDA tools. Dedicated to end-users of Siemens EDA solutions, this conference is free to attend and includes innovative keynotes from industry leaders, enriching technical sessions as well as a chance to network with colleagues and… Read More »User2User Europe 2024
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5 events,
TSMC Technology Workshop 2024 – Boston
TSMC Technology Workshop 2024 – Boston
08:30 – 09:30 Registration & Partner Pavilion 09:30 – 09:40 Welcome & Opening Remarks 09:40 – 10:00 Market Outlook – Powering AI Together 10:00 – 10:30 Advanced Technology Leadership 10:30 – 11:00 Coffee Break & Ecosystem Pavilion 11:00 – 11:25 Specialty Technology Leadership 11:25 – 11:50 Manufacturing Excellence 11:50 – 13:00 Lunch & Ecosystem Pavilion… Read More »TSMC Technology Workshop 2024 – Boston
AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
Antenna/RF design problems often involve the optimization of many variables, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent, accurate, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while increasing user productivity and efficiency. Leveraging an advanced AI-enabled methodology, the Cadence Optimality Intelligent System Explorer delivers… Read More »AI-Driven 3D System Analysis & Optimization for EM Antenna/RF Problems
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Cracking the Power Code: Innovative Approach to SoC Power Optimization
Power is the biggest factor impacting semiconductors from custom silicon to CPU/GPU products. System-level Power modeling and simulation is needed to measure power accurately and efficiently. The scope of power studies has expanded to include the software, thermal and generation to feed into the UVM/UPF methodology. At this Webinar we will highlight a new system-level… Read More »Cracking the Power Code: Innovative Approach to SoC Power Optimization
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Ansys – Simulation World 2024
Did you know that simulation helped Pratt & Whitney design a game-changing engine architecture that has saved aircraft operators over a million gallons in fuel? Or that sustainable energy start-up Amogy is using simulation to build a novel, portable, carbon-free energy system to convert ammonia into renewable fuel that will power green transportation solutions of the future? Or that… Read More »Ansys – Simulation World 2024
Introduction to the Open-source EDA Ecosystem
Introduction to the Open-source EDA Ecosystem
Open-source hardware in the European Chips Act Matthew Xuereb, European Commission Free and open-source semiconductor ecosystem Luca Alloatti, Free Silicon Foundation ETS Open-source EDA software and semiconductor design Jean-Paul Chaput, Sorbonne University, Coriolis Foundation European roadmap on the advancement of open-source EDA tools Rihards Novickis, Latvian Institute of Electronics and Computer Science
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Keysight EDA Connect Tour – Burlington
Keysight EDA Connect Tour – Burlington
As AI is redefining communication and connectivity, your ability to design, simulate, and test — using an intelligent and automated workflow — is what will set you apart. Join us for a half-day event that brings together top industry experts and innovators to explore modern RF circuit and system design, including advanced topics like phased… Read More »Keysight EDA Connect Tour – Burlington
AI-Driven EM-IR Design Closure
AI-Driven EM-IR Design Closure
IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology.… Read More »AI-Driven EM-IR Design Closure
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Embedded Vision Summit 2024
The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why Attend? It's a First-Rate Program with Powerful Insights into Practical Perceptual AI. Join us for three days of learning—from tutorials to Deep-Dive Day, covering the latest technical insights,… Read More »Embedded Vision Summit 2024
The Next Generation of 3DIC Interposer/InFO Design
The Next Generation of 3DIC Interposer/InFO Design
In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm, we seemingly… Read More »The Next Generation of 3DIC Interposer/InFO Design
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Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the AI application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the AI acceleration domain, and thus more… Read More »Accelerating AI Applications Using Custom RISC-V based SIMD/VLIW DSPs
Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
In 2021 Siemens EDA released CDC Assist. CDC Assist is an ML powered feature that empowers users to configure, debug, and close CDC on designs more rapidly. Following the success of CDC Assist, Siemens introduced RDC Assist in 2023. Using the same ML technology in CDC Assist, RDC Assist dramatically improves the time and… Read More »Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning