EDA
Events
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Accelerating DFT verification sign-off with the Questa DFT Verification Platform
Siemens EDA 46871 Bayside Parkway, Building B, Fremont, CA, United StatesAccelerating DFT verification sign-off with the Questa DFT Verification Platform This seminar will update you on technologies and techniques you can adopt to increase your DFT verification productivity today. Specifically, we will cover: Navigating the Growing Complexity of Design-for-Test and Evolving Verification Challenges Revolutionizing Test Strategies to deliver reliable products into HPC, Automotive, Aerospace,… Accelerating DFT verification sign-off with the Questa DFT Verification Platform
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Cocotb 2.0: Modernize your testbenches for even more productivity
Cocotb 2.0 is the latest major version of cocotb, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches, you can benefit from improved typing and less surprising corner cases. In this talk, we’ll show what’s new in cocotb 2.0, and how you can modernize your code bases… Cocotb 2.0: Modernize your testbenches for even more productivity
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The Development and Evolution of Verilog & SystemVerilog
Abstract: SystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities, constrained random testing (CRT), and functional coverage were all features that were added to SystemVerilog and incorporated into the Universal Verification Methodology (UVM). UVM has become the most dominant and… The Development and Evolution of Verilog & SystemVerilog
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DVCon Europe 2024
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyThe Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques,… DVCon Europe 2024
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ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted
There are so many options for Network-on-Chip: ARM-Corelink CMN700, Arteris FlexNoC, open-source NoC interconnect, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet, do we… ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted
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OSMOSIS 2024
Holiday Inn City Center Hochstraße 3, Munich, GermanyElevate your success with osmosis 2024 The annual osmosis event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. If you possess a compelling achievement narrative, we invite you… OSMOSIS 2024
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Static and Dynamic CDC Verification of AXI4 Stream-based IPs
The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP, capable of changing clock domains when… Static and Dynamic CDC Verification of AXI4 Stream-based IPs
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Jasper User Group San Jose 2024
Cadence Design Systems, Bldg 10 2655 Seeley Avenue, San Jose, CA, United StatesThe CadenceCONNECT: Jasper User Group San Jose will be held in person on October 22 - 23 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and… Jasper User Group San Jose 2024
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Hardware Verification using VirtuaLAB
VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times, running at high emulation speeds, integrated with Protocol Analyzer for complete protocol visibility and… Hardware Verification using VirtuaLAB
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ICCAD 2024
Newark Liberty International Airport Marriott 1 Hotel Rd, Newark, NJ, United StatesThe International Conference on Computer-Aided Design focuses on advancements and research in the field of electronic design automation (EDA) and computer-aided design (CAD) for integrated circuits and systems. Topics include innovations in design methodologies, tools, algorithms, and technologies related to the development of electronic systems. The International Conference on Computer-Aided Design focuses on advancements and… ICCAD 2024
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Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications
High Bandwidth Memory (HBM) has revolutionized AI, machine learning, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar, you will learn how… Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications
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ITC 2024
Hilton San Diego Bayfront 1 Park Blvd, San Diego, CA, United StatesInternational Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn… ITC 2024