ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe- Designing the interconnect is not for the weak-hearted

There are so many options for Network-on-Chip: ARM-Corelink CMN700, Arteris FlexNoC, open-source NoC interconnect, and of course developing home-grown fully customized solutions. Where does each solution fit? Where do we use it- backplane vs inside domains? How does AMBA AXI or PCIe or CXL fit in the mix? With the advent of chiplet, do we go with UCIe or bunch-of-wires. Where do we locate the DRAM and the task scheduler? Lots of questions need to be answered before the SoC or chiplets can be implemented.

In this Webinar, we will take the mystery out of these architecture decisions by demonstrating how system modeling can provide quantitative metrics to validate and optimize these requirements. For this purpose we will use the mapping of a CNN- Resnet 50 on an AI processor, Open Architecture Management (OAM) system, heterogeneous compute SoC-FPGA and development of a custom NoC.

To measure the quality of the design, we will show the running of standard and synthetic workloads. Quantitative metrics generated will include latency, throughput, buffer occupancy, peak power consumed, heat generated, cache hit-miss and memory bandwidth. We will also show how the source of bottlenecks can be identified. The design can be experimented with different routing schemes, schedulers, buffer size, clock speeds, flits, clock domains, flow control credit and quality-of-service.