IP
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Synopsys Technical Forum 2024
San Jose Marriott 301 S Market Street, San Jose, CA, United StatesPlease join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing's mask synthesis, mask data prep, and lithography simulation solutions. The Tech Forum is peer-to-peer, giving you the opportunity to hear how your lithography colleagues have… Synopsys Technical Forum 2024
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DVCon USA 2024
The DoubleTree by Hilton 2050 Gateway Place, San Jose, CA, United StatesThe Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees… DVCon USA 2024
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Navigating the Power Challenges of Datacenter Infrastructure
The surge in applications such as AI, HPC, and GPU-intensive workloads requires unparalleled performance, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency, reduce costs, and adhere to stringent environmental standards. Join us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel, Microsoft, Arm and proteanTecs. We will explore… Navigating the Power Challenges of Datacenter Infrastructure
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GSA International Semiconductor Conference
Here East 14 E Bay Lane, London, United KingdomInaugural GSA event in partnership with the UK Government. Meet senior business leaders, investors, and public policy officials from around the world. Across two days, join us for exciting discussions on semiconductor innovation for a NetZero economy, with a view on the dramatically changing supply chain, government interventions and industry outlook. Semiconductor Innovation for… GSA International Semiconductor Conference
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SNUG Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesConnecting the Synopsys User Community SNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts can meet, network, and share ideas about chip and system design. Technical Committee SNUG thanks the members of the Technical Committee who volunteer their time… SNUG Silicon Valley 2024
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RISC-V Instruction Set Architecture: Enhancing Computing Power
*Work email required for registration* Don't miss out on this exclusive opportunity to stay ahead in the rapidly evolving landscape of chip design. Join us for an engaging discussion that promises to inspire and inform: - Gain insights into the latest trends shaping chip design. - Learn from industry leaders about the strategies behind successful… RISC-V Instruction Set Architecture: Enhancing Computing Power
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Siemens EDA User2User Conference
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesEngineer a smarter future, faster at Siemens EDA User2User Conference April 3-4, 2024 Santa Clara, CA. Join your colleagues from around the industry for a day of technical sessions, networking, keynote sessions, labs and more. User2User is free of charge for Siemens EDA customers and includes sessions, lunch, and parking. Technology tracks covering the latest… Siemens EDA User2User Conference
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Embedded World 2024
NürnbergMesse Messezentrum 1, Nurnberg, GermanyThe embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight into the world of embedded systems, from components and modules to operating systems, hardware and software design, M2M communication, services, and various issues related to… Embedded World 2024
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Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the… Exploring the Advancement of Chiplet Technology and the Ecosystem
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CadenceLIVE Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings users, developers, and industry experts together to connect, share ideas, and inspire design creativity. Attendees have the opportunity… CadenceLIVE Silicon Valley 2024
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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP