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Marketing EDA

Freelance EDA Consultant
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    • Marketing EDA
    • SemiWiki.com
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    • DAC 2025
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12 events found.

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  • July 2024

  • Wed 17
    Synopsys, July 24, 2024
    July 17, 2024 @ 10:00 am - 11:00 am PDT

    Enhancing Manufacturing Test Flows with Synopsys VC Z01X

    Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll… Enhancing Manufacturing Test Flows with Synopsys VC Z01X

  • Wed 24
    Siemens, July 24, 2024
    July 24, 2024 @ 8:00 am - 9:00 am PDT

    Simulating AMD’s next-gen Versal Adaptive SoC devices using Questasim

    Versal Adaptive SoC, a revolutionary adaptable platform developed by AMD, integrates several key components such as the AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC), and a diverse array of specialized IPs. This innovative platform facilitates the efficient execution of intricate algorithms spanning from machine learning to high-performance computing tasks.… Simulating AMD’s next-gen Versal Adaptive SoC devices using Questasim

  • Wed 24
    EE Times, July 24-25, 2024
    July 24, 2024 @ 8:00 am - July 25, 2024 @ 5:00 pm PDT

    Chiplets: Building the Future of SoCs

    Chiplets, also known as heterogeneous multi-die systems, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries, particularly fueled by the widespread adoption of AI technology. However, while the concept of using chiplets to construct larger chips to overcome… Chiplets: Building the Future of SoCs

  • Thu 25
    Silvaco, July 25, 2024
    July 25, 2024 @ 10:00 am - 11:00 am PDT

    Applying Artificial Intelligence in Fab Technology Co-Optimization​​

    The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach. This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically, it can take weeks to months of experimentation, depending on what process parameters are… Applying Artificial Intelligence in Fab Technology Co-Optimization​​

  • August 2024

  • Tue 6
    Synopsys, August 6, 2024
    August 6, 2024 @ 10:00 am - 11:00 am PDT

    Fab.da: Comprehensive AI-Driven Process Analytics for Faster Ramp and Efficient High-Volume Manufacturing

    The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms, the complexity of the manufacturing process increases in response. To combat the complexity and sheer intricacy of semiconductor manufacturing, innovative software solutions are required. Synopsys Fab.da is a comprehensive process control solution that utilizes artificial intelligence (AI)… Fab.da: Comprehensive AI-Driven Process Analytics for Faster Ramp and Efficient High-Volume Manufacturing

  • Mon 12
    Scientific Analog, August 12,2024
    August 12, 2024 @ 3:00 pm - 4:00 pm PDT

    Modeling and Simulation of Silicon Photonics Systems in SystemVerilog

    Silicon photonics systems integrate photonic components such as optical waveguides, couplers, resonators, photodetectors, etc. along with electronic components on the same silicon chip to realize high-bandwidth, high-density, and low-power communication via wavelength-division multiplexing (WDM). This talk will address the challenges of modeling and simulating silicon photonics WDM transceivers in SystemVerilog, which contain photonic devices for… Modeling and Simulation of Silicon Photonics Systems in SystemVerilog

  • Thu 15
    Aldec, August 15, 2024
    August 15, 2024 @ 11:00 am - 12:00 pm PDT

    Why Should Our Team be Using VHDL + OSVVM for Verification?

    Abstract: This is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. Description: Developing and deploying a verification methodology can be costly… Why Should Our Team be Using VHDL + OSVVM for Verification?

  • Tue 20
    Ansys, August 20, 2024
    August 20, 2024 @ 11:00 am - 1:00 pm PDT

    Mastering EMC Simulations for Electronic Designs

    Overview Electromagnetic Compatibility (EMC) simulation is critical for ensuring that electronic devices comply with regulatory standards and perform optimally in their intended environments. As the complexity of electronic systems increases, the importance of EMC simulation grows, allowing engineers to predict and mitigate potential electromagnetic interference (EMI) issues before physical prototypes are built. For EMC and… Mastering EMC Simulations for Electronic Designs

  • Thu 22
    Aldec, August 22, 2024
    August 22, 2024 @ 11:00 am - 12:00 pm PDT

    Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

    European Session Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity… Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

  • Wed 28
    Cadence, August 28, 2024
    August 28, 2024 @ 8:00 am - 9:00 am PDT

    Design, Integrate, Analyze and Manage with Allegro X

    Designing PCBs in today’s world means using multiple tools to get the job done. The Allegro X Design Platform allows you to access all these tools in one unified design environment. Join us to discuss how you can reduce your cycle time, ensure product reliability and get first-time-right designs with Allegro X. Topics we’ll cover… Design, Integrate, Analyze and Manage with Allegro X

  • Thu 29
    Silvaco, August 29, 2024
    August 29, 2024 @ 10:00 am - 11:00 am PDT

    Micron Utilizes Silvaco’s Fab Technology Co-Optimization for Development and Manufacturing of Memory Technologies

    Memory products from Micron Technology, such as DRAM components and 3D NAND, are propelling the advancement of process technologies. Innovative modeling methods are required to tackle the complexities in fabricating structures and to evaluate process variation effects on electrical performance. This webinar highlights how Micron Technology utilizes Silvaco’s Fab Technology Co-Optimization (FTCOTM) platform for the… Micron Utilizes Silvaco’s Fab Technology Co-Optimization for Development and Manufacturing of Memory Technologies

  • September 2024

  • Tue 3
    DVClub Europe 2024
    September 3, 2024 @ 12:00 pm - 1:00 pm BST

    DVClub Europe – September 2024

    This DVClub event will have talks on verification of low power features of VLSI designs, discussing strategies for accurately measuring power consumption and ensuring that power-saving mechanisms are effective. Additionally, speakers will share insights on how to simulate and analyze different power scenarios to identify potential issues and optimize power management techniques. Attendees will have… DVClub Europe – September 2024

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Daniel Payne Follow 9,349 1,924

Daniel_J_Payne
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
8 Dec 1998127956322119795

What's new with Integrated Product Lifecycle Management (IPLM)? My blog about Perforce at #SemiWiki, #SemiEDA

Image for twitter card

What’s New with Integrated Product Lifecycle Management - Semiwiki

I’ve blogged about Methodics before they were acquired by Perforce…

semiwiki.com

Reply on Twitter 1998127956322119795 Retweet on Twitter 1998127956322119795 1 Like on Twitter 1998127956322119795 1 Twitter 1998127956322119795
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
1 Dec 1995564555926470911

Transforming functional verification through intelligence, a blog about Questa One from Siemens on #SemiWiki #SemiEDA

Image for twitter card

Transforming Functional Verification through Intelligence - Semiwiki

SoC projects are running behind schedule as design and verification…

semiwiki.com

Reply on Twitter 1995564555926470911 Retweet on Twitter 1995564555926470911 0 Like on Twitter 1995564555926470911 0 Twitter 1995564555926470911
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
28 Nov 1994512627268292749

Just added SpiceGenTcl to our list of open source #SemiEDA tools at #SemiWiki, it lets you control Ngspice and Xyce using Tcl. https://semiwiki.com/wikis/industry-wikis/eda-open-source-tools-wiki/

Image for the Tweet beginning: Just added SpiceGenTcl to our Twitter feed image.
Reply on Twitter 1994512627268292749 Retweet on Twitter 1994512627268292749 0 Like on Twitter 1994512627268292749 0 Twitter 1994512627268292749
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
17 Nov 1990515272583966937

Boosting SoC design productivity with IP-XACT, a #SemiEDA and #SemiIP blog at #SemiWiki with input from Accellera. https://semiwiki.com/semiconductor-services/363741-boosting-soc-design-productivity-with-ip-xact/

Image for the Tweet beginning: Boosting SoC design productivity with Twitter feed image.
Reply on Twitter 1990515272583966937 Retweet on Twitter 1990515272583966937 0 Like on Twitter 1990515272583966937 0 Twitter 1990515272583966937
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Address:

10440 SW Kellogg Drive
Tualatin, OR 97062

SemiWiki Blogs

© 2025 Marketing EDA | All Rights Reserved

Site by Tualatin Web

Daniel Payne Follow 9,349 1,924

Daniel_J_Payne
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
8 Dec 1998127956322119795

What's new with Integrated Product Lifecycle Management (IPLM)? My blog about Perforce at #SemiWiki, #SemiEDA

Image for twitter card

What’s New with Integrated Product Lifecycle Management - Semiwiki

I’ve blogged about Methodics before they were acquired by Perforce…

semiwiki.com

Reply on Twitter 1998127956322119795 Retweet on Twitter 1998127956322119795 1 Like on Twitter 1998127956322119795 1 Twitter 1998127956322119795
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
1 Dec 1995564555926470911

Transforming functional verification through intelligence, a blog about Questa One from Siemens on #SemiWiki #SemiEDA

Image for twitter card

Transforming Functional Verification through Intelligence - Semiwiki

SoC projects are running behind schedule as design and verification…

semiwiki.com

Reply on Twitter 1995564555926470911 Retweet on Twitter 1995564555926470911 0 Like on Twitter 1995564555926470911 0 Twitter 1995564555926470911
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
28 Nov 1994512627268292749

Just added SpiceGenTcl to our list of open source #SemiEDA tools at #SemiWiki, it lets you control Ngspice and Xyce using Tcl. https://semiwiki.com/wikis/industry-wikis/eda-open-source-tools-wiki/

Image for the Tweet beginning: Just added SpiceGenTcl to our Twitter feed image.
Reply on Twitter 1994512627268292749 Retweet on Twitter 1994512627268292749 0 Like on Twitter 1994512627268292749 0 Twitter 1994512627268292749
Daniel_J_Payne avatar Daniel Payne @Daniel_J_Payne ·
17 Nov 1990515272583966937

Boosting SoC design productivity with IP-XACT, a #SemiEDA and #SemiIP blog at #SemiWiki with input from Accellera. https://semiwiki.com/semiconductor-services/363741-boosting-soc-design-productivity-with-ip-xact/

Image for the Tweet beginning: Boosting SoC design productivity with Twitter feed image.
Reply on Twitter 1990515272583966937 Retweet on Twitter 1990515272583966937 0 Like on Twitter 1990515272583966937 0 Twitter 1990515272583966937
Load More

Address:

10440 SW Kellogg Drive
Tualatin, OR 97062

SemiWiki Blogs

© 2025 Marketing EDA | All Rights Reserved

Site by Tualatin Web