Webinar
Events
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Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim
Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process. Learn how the latest innovations in QuestaSim address these challenges by enabling full off-line…
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Streamline MMIC Design Efficiency with Intelligent Design Data Management
In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? Trusted by hundreds of IC design organizations…
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Exploring the Advancement of Chiplet Technology and the Ecosystem
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the…
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Introduction to ParagonX
Are you ready to supercharge your design process? Introducing our Diakopto Training Program - your gateway to a faster, easier, and more intuitive approach to design analysis and optimization! In this course, you'll learn how to: Analyze and visualize layout parasitics with precision using R/C/delay/I maps. Perform net matching for accurate and refined designs. Identify…
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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling…
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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect protocol models, and multiple coherent and non-coherent compute resources. This Webinar will demonstrate a methodology for rapid modeling and architecture trade-off using UCIe in modeling…
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DVClub Europe – Formal Verification
13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of "Formal Verification". Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting…
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Deploying Solido Design Environment AI Workflows on AWS
Utilizing AWS cloud resources to accelerate variation-aware verification AI-powered Solido Design Environment provides SPICE-accurate variation-aware verification for 3, 4, 5, 6 and higher sigma targets, orders of magnitude faster than traditional brute-force methods. With cloud computing made more accessible than before, many teams are considering running design and verification workloads, including Solido Design Environment, on…
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The Era of Software-Defined Everything: Chiplets and Bespoke Silicon
From fintech to automotive, defense to healthcare, everyone wants bespoke computing platforms to build "software-defined solutions" that are differentiated in their respective markets. Sign up and save your spot for this special presentation. Overview With the advent of 3D ICs and heterogeneous semiconductor integration, mapping a system on a customized chip/hardware is accessible to "everyone.”…
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Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions
Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. Join us on Thursday, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. Overview Accurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation, which can address various physical interactions and phenomena. By…
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DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1,…
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Smart methods for DFT chip architecture & validation
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs. The…