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SemIsrael Tech Webinar
11:00 - 11:30 | ASIC Verification Veloce proFPGA: The Perfect Complement for Your System Verification Flow 11:30 - 12:00 | Emulation Queuing Emulation - Getting a Better Return on Your Investment 12:00 - 12:30 | DFT For Automotive Design-For-Test Design (DFT) Consideration for Automotive Designs 12:30 - 13:00 | Low-power Vector AI Processing Introducing SiFive… SemIsrael Tech Webinar
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ISQED Symposium 2022
The 23rd International Symposium on Quality Electronic Design (ISQED'22) is the premier interdisciplinary and multidisciplinary Electronic Design conference—bridges the gap among Electronic/Semiconductor ecosystem members providing electronic design tools, integrated circuit technologies, semiconductor technology,packaging, assembly & test to achieve total design quality. Current and all past ISQED events have been held with the technical sponsorship of IEEE CASS, IEEE… ISQED Symposium 2022
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CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise. In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive… CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
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Formal Verification for non-specialists
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-qualified engineers seem reluctant to go beyond simplified formal "apps". So, what is the truth of the matter? Can non-specialist engineers become productive with formal? In… Formal Verification for non-specialists
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SystemC Evolution Fika – Parallelization of SystemC simulations
In 2022 we are continuing the SystemC Evolution by organizing a series of online workshops to discuss the latest SystemC developments and applications. We refer to these workshops as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about. Organization Team Ola Dahl, Ericsson… SystemC Evolution Fika – Parallelization of SystemC simulations
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Design Automation WebiNar (DAWN)
We are thrilled to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. Due to the outbreak of coronavirus (COVID-19), almost all… Design Automation WebiNar (DAWN)
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The Changing Landscape of Automotive Electronics
The automotive industry is undergoing a seismic shift. Supply chain constraints, software defined architectures, functional safety requirements, and the changing dynamics between OEMs, Tier 1s and semiconductor companies, are driving the industry to seek innovative ways to approach new challenges. Join us on Tuesday, April 12th, 2022, for a special panel discussion as we review… The Changing Landscape of Automotive Electronics
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Design Methodology for Building Power Efficient RTL
The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically translate to efficiency gains in terms of energy anymore. That’s why regardless of the application area - networking, computation, or… Design Methodology for Building Power Efficient RTL
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Methodics User Group (MUG) – April 12, 2022
If your company uses 3rd party IP in their design process, it is important to consider how you will manage them to extract maximum leverage. Having a central library and consistent processes for managing both internal and 3rd party IP is vital step to get the most your investment. Learn how you can optimize 3rd… Methodics User Group (MUG) – April 12, 2022
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Synopsys Parasitic Extraction – Interconnect 2022
Why Attend? Join us at the upcoming SPEX-I 2022 Workshops to learn about the latest features and flows to address signoff parasitic extraction challenges for advanced digital SoC designs or complex custom designs using Synopsys’ StarRC™ solution. In this workshop, we will discuss key methods to improve design convergence, demonstrate newer technologies to improve TAT,… Synopsys Parasitic Extraction – Interconnect 2022
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In-Design EM Analysis for Microwave/RF Design and Verification Workflows
Overview 3D finite element method (FEM) and 3D planar method of moments (MoM) have become a standard design practice for ensuring the accuracy of the overall network simulation. However, without proper setup and use of electromagnetic (EM) analysis tools to define the structure and RF excitation (ports), designers can experience erroneous simulation results and/or excessively… In-Design EM Analysis for Microwave/RF Design and Verification Workflows
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Running CDC Analysis with Xilinx Parameterized Macros
Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and BRAM… Running CDC Analysis with Xilinx Parameterized Macros
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