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CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

April 6 @ 10:00 am - 11:00 am PDT

Cadence, Multi-Chiplet

Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.

In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive design re-spins. Therefore, it is important to have a vision of thermal gradients, signal quality, and power delivery across chiplets, packages, and PCBs to not only address any risks, but also optimize the design’s TSV locations for maximum performance.

Details

Date:
April 6
Time:
10:00 am - 11:00 am PDT
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Organizer

Cadence
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