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Debugging Features of UVM
A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging. There are various debugging features built into UVM to help with this. In this webinar, Doulos Senior Member Technical Staff, Doug… Debugging Features of UVM
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TSMC 2022 Technology Symposium – North America
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesA Technology Symposium (In-Person Event) Date: June 16, 2022 (Thursday) Time: 8:30a.m. - 5:05p.m. Venue: Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA 95054 NA Technology Symposium (Online VOD Event) Date: June 30, 2022 (Thursday) Website link to be announced in June Get the latest on: TSMC's smartphone, HPC, IoT, and automotive… TSMC 2022 Technology Symposium – North America
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Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
Join this Synopsys webinar to learn how to perform large-scale, accurate and reliable Density Functional Theory (DFT) simulations with the QuantumATK platform: Discover how to perform accurate and reliable large scale DFT simulations even at the hybrid functional level - with Linear Combination of Atomic Orbital basis set using modest computational resources. Learn how to… Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
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Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows create a serious risk of product… Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
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OSVVM’s Test Reports and Simulator Independent Scripting
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay… OSVVM’s Test Reports and Simulator Independent Scripting
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ASYNC 2022 Summer School: Physical Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… ASYNC 2022 Summer School: Physical Design
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TSMC 2022 Technology Symposium – Europe
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsEurope Technology Symposium (In-Person Event) Date June 20, 2022 (Monday) Time 8:30a.m. - 4:50p.m. Venue Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701Amsterdam,1118BN Netherlands Israel Technology Workshop (In-Person Event) Date June 28, 2022 (Tuesday) Time 9:30a.m. - 4:30p.m. Venue Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, Israel Europe Technology Symposium (Online VOD Event) Date June… TSMC 2022 Technology Symposium – Europe
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Leti Innovation Days
Minalogic 3 PARV Louis Neel, Grenoble, FranceThe chip shortage has brought with it an extraordinary boost to Moore's Law. Discover policy maker and tech leader strategic decisions on downscaling, "More than Moore electronics" and other future technologies for components. Identify key emerging technologies to grow your business. Plenary Session A plenary session will gather high-level keynote speakers to discuss novel tech strategies… Leti Innovation Days
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Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog's… Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
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Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
Standards such as ISO 26262 define strict requirements, processes, and methods that all stakeholders – IP vendors, sub-system developers, and semiconductor SoC and system developers – must abide by when designing safety-critical automotive products. One such requirement is the Development Interface Agreement (DIA), which defines the interactions, interfaces, responsibilities, dependencies, and work products exchanged between… Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
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Cost effective 5G for the IoT
5G RedCap is an exciting new 3GPP feature, soon to be introduced in Rel. 17 of the standard, targeting reduced capability use cases for industrial, wearables, and IoT in general. We will discuss the new standard, the market potential, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. Join CEVA to learn about: Introduction to the… Cost effective 5G for the IoT
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Extending Processors into Flexible Accelerators for 5G
The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the… Extending Processors into Flexible Accelerators for 5G
12 events found.