Calendar of Events
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1 event,
ISCAS 2022
The IEEE International Symposium on Circuits and Systems (ISCAS) ISCAS 2022 will be held in Austin Texas from May 28 through June 1. Austin is one of the fastest growing cities in the United States. Much of this growth is attributable to the rapidly growing tech sector in the Austin metropolitan area. The large and… Read More »ISCAS 2022
1 event,
4 events,
RISC-V Days Tokyo 2022 Spring
RISC-V Days Tokyo is Japan’s largest online RISC-V event. Live online presentations are hosted on May 31st (Tue), June 1st (Wed) and 2nd (Thu). There will also be a virtual “RISC-V Pavilion” for the last two days. RISC-V Days Tokyo aims to bring together leading RISC-V technologies and products, key persons and engineers, and to… Read More »RISC-V Days Tokyo 2022 Spring
2022 IEEE 72nd Electronic Components and Technology Conference
The Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the IEEE Electronics Packaging Society. Abstract Submission is Open | Subscribe to our mailing list
ITherm 2022
Welcome to ITherm 2022 The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems May 31 - June 3, 2022 Sheraton Hotel & Marina San Diego, CA USA (Co-Located with ECTC) Sponsored by the IEEE's Electronics Packaging Society (EPS), ITherm 2022 is an international conference for scientific and engineering exploration of thermal, thermomechanical and emerging… Read More »ITherm 2022
6 events,
Automotive Ethernet Congress
WELCOME POWERFUL NETWORK FOR THE COMPUTER ON WHEELS The Automotive Ethernet Congress will take place for the eighth time on June 1 - 2, 2022. The conference program will highlight the entire spectrum of topics relating to the use of Ethernet in vehicles. The vehicle is undergoing the greatest change since its inception. Automation, networking, and digitalization of the… Read More »Automotive Ethernet Congress
Become an SVA Expert in One Hour
Become an SVA Expert in One Hour
Doulos Co-Founder & Technical Fellow John Aynsley will teach the core principles necessary to understand and use SystemVerilog Assertions, focussing on the aspects of SVA that are applicable to both formal verification and simulation. Particular emphasis will be placed on the core semantics of temporal logic so that you will be able to write your own assertions,… Read More »Become an SVA Expert in One Hour
1 event,
ASYNC 2022 Summer School: Behavioral Design
ASYNC 2022 Summer School: Behavioral Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… Read More »ASYNC 2022 Summer School: Behavioral Design
1 event,
Embedded Applications Get a Helping Hand: Extensible Processor Architectures
Embedded Applications Get a Helping Hand: Extensible Processor Architectures
Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial intelligence (AI), automotive and storage segments require increased bandwidth and memory address space expansion. As Moore’s law slows, design teams seek different ways… Read More »Embedded Applications Get a Helping Hand: Extensible Processor Architectures
3 events,
CadenceLIVE 2022 – Silicon Valley
Are you driving design change or feel you’ve overcome challenges that could impact the electronic revolution? CadenceLIVE™ offers you an opportunity to tell your story. Showcase your expertise and offer tips to address the complexities and challenges that engineers face today. CadenceLIVE Silicon Valley features peer presentations that highlight solutions, using Cadence® products, for today’s… Read More »CadenceLIVE 2022 – Silicon Valley
Customers Discuss Their Real World Use of High-Level Synthesis
Summary The focus of this seminar is to have real-world customers present their successes using Catapult High-Level Synthesis (HLS) in markets such as Automotive, 5G/Communications, Video/Imaging, AI/ML, and MEMs Sensors. The companies who will be presenting are: Google (Video/Imaging) NASA-JPL (Video/Imaging) NVIDIA (Video/Imaging) NVIDIA Research (AI/ML) NXP Semiconductors (Automotive) STMicroelectronics (MEMS Sensors) Viosoft (5G/Communications) In… Read More »Customers Discuss Their Real World Use of High-Level Synthesis
From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
Today, most of the software functions in a car can be tested efficiently using virtual ECU models and DevOps engineering methods. However, final acceptance tests with real vehicles are still mandatory, even though they are expensive and time-consuming. The prevalent problem is the gap between automated virtual methods and manual testing, which further increases costs… Read More »From Virtual ECU to Real Vehicle: Continuous Testing of Functional Requirements
5 events,
5X Faster Equivalence Checking with Formality ML-driven DPX
5X Faster Equivalence Checking with Formality ML-driven DPX
Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation from production quality Equivalence checking is to be able to complete verification with minimal efforts and the fastest turn-around-time. This presentation… Read More »5X Faster Equivalence Checking with Formality ML-driven DPX
How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
Image retention is a long-standing issue in the display community. To effectively solve this issue, or even to minimize its impact on their products, display manufacturers and consumer electronics vendors need to simulate this effect at the SPICE level. However, image retention is a result of dynamic device effects that cannot be modeled by other… Read More »How to Eliminate Image Retention Issues with SmartSpice Flex Modeling
Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC)… Read More »Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
1 event,
2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY AND CIRCUITS
In-person with on-demand content The 2022 IEEE Symposium on VLSI Technology and Circuits will be organized as a hybrid event with both live sessions on-site in the Hilton Hawaiian Village to enable networking opportunities, and on-demand sessions to allow access to selected talks and panels to those who cannot travel. The five-day event will include:… Read More »2022 IEEE SYMPOSIUM ON VLSI TECHNOLOGY AND CIRCUITS
2 events,
ASYNC 2022 Summer School: Gate-level Design
ASYNC 2022 Summer School: Gate-level Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… Read More »ASYNC 2022 Summer School: Gate-level Design
3 events,
Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows provide a serious risk for product… Read More »Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
As boards become smaller and faster, the environment for thermal issues becomes increasingly challenging. The thermal management of significant resistive losses in PCB and package structures is critical, especially because these resistive losses are also temperature-dependent, making dynamic and static IR drop analysis crucial in addressing the performance and capacity challenges of such designs. Join… Read More »How Static and Dynamic IR Drop Analysis Can Help PCB Designs Challenges
3 events,
Debugging Features of UVM
Debugging Features of UVM
A UVM testbench is a large and complex piece of software. At some stage, like any other large and complex piece of software, a verification environment written using UVM is going to require debugging. There are various debugging features built into UVM to help with this. In this webinar, Doulos Senior Member Technical Staff, Doug… Read More »Debugging Features of UVM
Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
Electronic systems in automobiles are growing rapidly in size, complexity, and critical functionality. As a result, functional safety verification is emerging as an essential requirement for automotive SoC and IP designs. In order to assure that even the most stringent safety standards are met at a faster pace, comprehensive and fast fault injection and simulation… Read More »Functional Verification to Fault Simulation: Considerations and Efficient Bring-Up
5 events,
TSMC 2022 Technology Symposium – North America
TSMC 2022 Technology Symposium – North America
A Technology Symposium (In-Person Event) Date: June 16, 2022 (Thursday) Time: 8:30a.m. - 5:05p.m. Venue: Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA 95054 NA Technology Symposium (Online VOD Event) Date: June 30, 2022 (Thursday) Website link to be announced in June Get the latest on: TSMC's smartphone, HPC, IoT, and automotive… Read More »TSMC 2022 Technology Symposium – North America
Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
Join this Synopsys webinar to learn how to perform large-scale, accurate and reliable Density Functional Theory (DFT) simulations with the QuantumATK platform: Discover how to perform accurate and reliable large scale DFT simulations even at the hybrid functional level - with Linear Combination of Atomic Orbital basis set using modest computational resources. Learn how to… Read More »Large-Scale and Accurate Density Functional Theory (DFT) Simulations with QuantumATK
OSVVM’s Test Reports and Simulator Independent Scripting
OSVVM’s Test Reports and Simulator Independent Scripting
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay… Read More »OSVVM’s Test Reports and Simulator Independent Scripting
1 event,
International Microwave Symposium
IMS is the flagship event in a week dedicated to all things microwaves and RF. The week also includes the IEEE MTT-S Radio Frequency Integrated Circuits Symposium (RFIC) and the Automatic Radio Frequency Techniques Group (ARFTG).
4 events,
Leti Innovation Days
The chip shortage has brought with it an extraordinary boost to Moore's Law. Discover policy maker and tech leader strategic decisions on downscaling, "More than Moore electronics" and other future technologies for components. Identify key emerging technologies to grow your business. Plenary Session A plenary session will gather high-level keynote speakers to discuss novel tech strategies… Read More »Leti Innovation Days
ASYNC 2022 Summer School: Physical Design
ASYNC 2022 Summer School: Physical Design
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using… Read More »ASYNC 2022 Summer School: Physical Design
TSMC 2022 Technology Symposium – Europe
TSMC 2022 Technology Symposium – Europe
Europe Technology Symposium (In-Person Event) Date June 20, 2022 (Monday) Time 8:30a.m. - 4:50p.m. Venue Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701Amsterdam,1118BN Netherlands Israel Technology Workshop (In-Person Event) Date June 28, 2022 (Tuesday) Time 9:30a.m. - 4:30p.m. Venue Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, Israel Europe Technology Symposium (Online VOD Event) Date June… Read More »TSMC 2022 Technology Symposium – Europe
5 events,
NAFEMS Americas Conference 2022
NAFEMS Americas will be hosting its biennial regional conference, formerly known as CAASE, on June 21-23, 2022, face-to-face, at the Indiana Convention Center in Indianapolis, Indiana! The NAFEMS Americas Regional Conference 2022 (NRC22 Americas) will bring together the leading visionaries, developers, and practitioners of CAE-related technologies in an open forum, unlike any other, to share experiences, discuss relevant trends,… Read More »NAFEMS Americas Conference 2022
Embedded World 2022
Whether it's the safety of electronic systems, distributed intelligence, the Internet of Things or e-mobility and energy efficiency – the embedded world trade fair lets you experience the whole world of embedded systems. Discover the innovations of the embedded sector, meet experts and win new customers. embedded world offers the entire spectrum – from components,… Read More »Embedded World 2022
Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog's… Read More »Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
6 events,
Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
Standards such as ISO 26262 define strict requirements, processes, and methods that all stakeholders – IP vendors, sub-system developers, and semiconductor SoC and system developers – must abide by when designing safety-critical automotive products. One such requirement is the Development Interface Agreement (DIA), which defines the interactions, interfaces, responsibilities, dependencies, and work products exchanged between… Read More »Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs
Cost effective 5G for the IoT
Cost effective 5G for the IoT
5G RedCap is an exciting new 3GPP feature, soon to be introduced in Rel. 17 of the standard, targeting reduced capability use cases for industrial, wearables, and IoT in general. We will discuss the new standard, the market potential, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. Join CEVA to learn about: Introduction to the… Read More »Cost effective 5G for the IoT
Extending Processors into Flexible Accelerators for 5G
Extending Processors into Flexible Accelerators for 5G
The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the… Read More »Extending Processors into Flexible Accelerators for 5G
5 events,
Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock switching elements or each sequential or combinatorial component, clock output of which becomes asynchronous with respect to the clock input… Read More »Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Advances in OSVVM’s Verification Data Structures
Advances in OSVVM’s Verification Data Structures
OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage,… Read More »Advances in OSVVM’s Verification Data Structures
5 events,
PIC International Conference
The 6th PIC International conference will build on the success of its predecessors, with industry-leading insiders delivering more than 30 presentations spanning four sectors. Attendees at the two-day conference will gain an up-to-date overview of the status of the global photonics industry, and will have the opportunity to meet many other key players within the… Read More »PIC International Conference
Balancing analog layout parasitics in MOSFET differential pairs
Balancing analog layout parasitics in MOSFET differential pairs
We have another #Pulsic webinar coming soon! This time we are taking a good look into MOSFET differential pairs with Paul Clewes. In this webinar, Paul will look at how to achieve a carefully balanced differential pair layout and consider the layout effects that impact the performance of a differential pair. Along the way, Paul will demonstrate… Read More »Balancing analog layout parasitics in MOSFET differential pairs
TSMC 2022 Technology Symposium – Israel
TSMC 2022 Technology Symposium – Israel
Israel Technology Workshop (In-Person Event) Date June 28, 2022 (Tuesday) Time 9:30a.m. - 4:30p.m. Venue Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, Israel Europe Technology Symposium (Online VOD Event) Date June 30, 2022 (Thursday) Website link to be announced in June Get the latest on: TSMC’s smartphone, HPC, IoT, and automotive platform solutions TSMC’s… Read More »TSMC 2022 Technology Symposium – Israel
Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
As the optical transceiver market moves from 400GBs to 800GBs, many complex analog components are required to assemble energy efficient and cost-effective optical modules. At this joint webinar we will use an 800G-DR8 PIC design case study to show how to accurately develop Photonic Integrated Circuit (PIC) designs with a focus on co-simulating and synthesizing… Read More »Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
2 events,
Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
Most safety critical SoCs, such as those developed for automotive driver aid systems, require ASIL-D compliance. ASIL-D is the highest grade in the ISO 26262 Standard’s risk classification system, required less than 1% Single Point Fault. According to the ISO 26262 Standard, fault campaign on the targeted designs is the recommended methodology to generate FMEDA… Read More »Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
3 events,
TSMC 2022 Technology Symposium – China, Virtual
TSMC 2022 Technology Symposium – China, Virtual
Date June 30, 2022 (Thursday) Time Starts at 9:00 a.m. Website link to be announced in June Get the latest on: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and… Read More »TSMC 2022 Technology Symposium – China, Virtual
Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
Designers of flat panel displays and detectors often rely on a variety of point tools from different EDA vendors that make the design flow discontinuous and difficult to integrate. These challenges, together with specific advanced display technology requirements, are addressed by the seamless and unique Silvaco TCAD-EDA flow. This webinar highlights how leading display and… Read More »Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
Introduction to OpenCPI (US)
Introduction to OpenCPI (US)
The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing technologies including GPPs (general purpose processors), FPGA (field programmable gate arrays), and GPUs (graphics processing units) assembled into mixed systems.… Read More »Introduction to OpenCPI (US)
1 event,
RIOS Open-source Hardware IP Licensing and Policy Workshop
RIOS Open-source Hardware IP Licensing and Policy Workshop
IOS Lab is excited to announce that the first international legal conference on open tech and IP will be held on July 1st, 2022 (GMT+8). The main themes of the 2022 conference are open hardware licensing, litigation protections and open source policies. Some of the most prominent and high-profile speakers and representatives from a wide… Read More »RIOS Open-source Hardware IP Licensing and Policy Workshop