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  • Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

    Learn how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog's… Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

  • Embedded World 2022

    Exhibition Centre Nuremberg Nuremberg, Germany

    Whether it's the safety of electronic systems, distributed intelligence, the Internet of Things or e-mobility and energy efficiency – the embedded world trade fair lets you experience the whole world of embedded systems. Discover the innovations of the embedded sector, meet experts and win new customers. embedded world offers the entire spectrum – from components,… Embedded World 2022

  • NAFEMS Americas Conference 2022

    Indianapolis Convention Center 1861 Monument Circle, Indianapolis, IN, United States

    NAFEMS Americas will be hosting its biennial regional conference, formerly known as CAASE, on June 21-23, 2022, face-to-face, at the Indiana Convention Center in Indianapolis, Indiana! The NAFEMS Americas Regional Conference 2022 (NRC22 Americas) will bring together the leading visionaries, developers, and practitioners of CAE-related technologies in an open forum, unlike any other, to share experiences, discuss relevant trends,… NAFEMS Americas Conference 2022

  • Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs

    Standards such as ISO 26262 define strict requirements, processes, and methods that all stakeholders – IP vendors, sub-system developers, and semiconductor SoC and system developers – must abide by when designing safety-critical automotive products. One such requirement is the Development Interface Agreement (DIA), which defines the interactions, interfaces, responsibilities, dependencies, and work products exchanged between… Simplify & Streamline Development of ISO 26262 Compliant Automotive SoCs

  • Cost effective 5G for the IoT

    5G RedCap is an exciting new 3GPP feature, soon to be introduced in Rel. 17 of the standard, targeting reduced capability use cases for industrial, wearables, and IoT in general. We will discuss the new standard, the market potential, and CEVA’s new PentaG2-Lite comprehensive baseband modem solution. Join CEVA to learn about: Introduction to the… Cost effective 5G for the IoT

  • Extending Processors into Flexible Accelerators for 5G

    The slowing down of Moore’s law and Dennard scaling has triggered an increased interest in application-specific instruction set processors (ASIPs). ASIPs implement a specialized instruction set architecture (ISA) tailored to the application and can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the… Extending Processors into Flexible Accelerators for 5G

  • Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis

    Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock switching elements or each sequential or combinatorial component, clock output of which becomes asynchronous with respect to the clock input… Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis

  • Advances in OSVVM’s Verification Data Structures

    OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage,… Advances in OSVVM’s Verification Data Structures

  • Balancing analog layout parasitics in MOSFET differential pairs

    We have another #Pulsic webinar coming soon! This time we are taking a good look into MOSFET differential pairs with Paul Clewes. In this webinar, Paul will look at how to achieve a carefully balanced differential pair layout and consider the layout effects that impact the performance of a differential pair. Along the way, Paul will demonstrate… Balancing analog layout parasitics in MOSFET differential pairs

  • TSMC 2022 Technology Symposium – Israel

    Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, Israel

    Israel Technology Workshop (In-Person Event) Date June 28, 2022 (Tuesday) Time 9:30a.m. - 4:30p.m. Venue Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, Israel Europe Technology Symposium (Online VOD Event) Date June 30, 2022 (Thursday) Website link to be announced in June Get the latest on: TSMC’s smartphone, HPC, IoT, and automotive platform solutions TSMC’s… TSMC 2022 Technology Symposium – Israel

  • Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers

    As the optical transceiver market moves from 400GBs to 800GBs, many complex analog components are required to assemble energy efficient and cost-effective optical modules. At this joint webinar we will use an 800G-DR8 PIC design case study to show how to accurately develop Photonic Integrated Circuit (PIC) designs with a focus on co-simulating and synthesizing… Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers