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Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
As the optical transceiver market moves from 400GBs to 800GBs, many complex analog components are required to assemble energy efficient and cost-effective optical modules. At this joint webinar we will use an 800G-DR8 PIC design case study to show how to accurately develop Photonic Integrated Circuit (PIC) designs with a focus on co-simulating and synthesizing… Develop and Verify Designs Using a Silicon Photonics Platform with Integrated Lasers
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SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
A Physically Unclonable Function or PUF is a function used to generate secret information on-chip. Information such as a secret key / public key pair may be generated on-chip each time it is needed, while the secret key never needs to be output from the chip. Thus the attack surface is reduced, since only the… SecuryzrTM iSSP: Simplifying security lifecycle management with PUF
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Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
Most safety critical SoCs, such as those developed for automotive driver aid systems, require ASIL-D compliance. ASIL-D is the highest grade in the ISO 26262 Standard’s risk classification system, required less than 1% Single Point Fault. According to the ISO 26262 Standard, fault campaign on the targeted designs is the recommended methodology to generate FMEDA… Optimizing Fault Simulations with Formal Analysis to Achieve ASIL Compliance for Automotive Designs
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TSMC 2022 Technology Symposium – China, Virtual
Date June 30, 2022 (Thursday) Time Starts at 9:00 a.m. Website link to be announced in June Get the latest on: TSMC's smartphone, HPC, IoT, and automotive platform solutions TSMC's advanced technology progress on 5nm, 4nm, 3nm processes and beyond TSMC's specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and… TSMC 2022 Technology Symposium – China, Virtual
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Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
Designers of flat panel displays and detectors often rely on a variety of point tools from different EDA vendors that make the design flow discontinuous and difficult to integrate. These challenges, together with specific advanced display technology requirements, are addressed by the seamless and unique Silvaco TCAD-EDA flow. This webinar highlights how leading display and… Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors
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Introduction to OpenCPI (US)
The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing technologies including GPPs (general purpose processors), FPGA (field programmable gate arrays), and GPUs (graphics processing units) assembled into mixed systems.… Introduction to OpenCPI (US)
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RIOS Open-source Hardware IP Licensing and Policy Workshop
IOS Lab is excited to announce that the first international legal conference on open tech and IP will be held on July 1st, 2022 (GMT+8). The main themes of the 2022 conference are open hardware licensing, litigation protections and open source policies. Some of the most prominent and high-profile speakers and representatives from a wide… RIOS Open-source Hardware IP Licensing and Policy Workshop
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22nd IEEE Nano
Edificio Gaspar Melchor de Jovellanos Carrer Eivissa, s/n, 07120 Palma, Illes Balears, SpainThe 22nd IEEE International Conference on Nanotechnology (IEEE-NANO 2022) will be held from 4th to 8th of July, 2022, at the Campus of Balearic Islands University (UIB) in Palma, the capital of Balearic Islands, Spain. IEEE-NANO is the flagship IEEE international conference on Nanotechnology, which has been a successful annual conference since 2001. Recent conferences were held… 22nd IEEE Nano
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FPGA-Conference Europe
Hotel NH München Ost Conference Center Einsteinring 20, Munich, Aschheim, GermanyFPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is addressing that progress across all major manufacturers. It focusses on user-oriented, practically applicable solutions that developers can quickly integrate into… FPGA-Conference Europe
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FSiC 2022 – Free Silicon Conference
Sorbenne Université 15-21 Rue de l'École de Médecine, Paris, FranceThe 2022 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 7,8,9 2022 (Thursday to Saturday). This event will build on top of the 2019 edition. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will… FSiC 2022 – Free Silicon Conference
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Driving Low-Power Design with High-Level Synthesis
With the growth in computing at the edge driven by the explosion of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed to reduce power. Since many of the low-power design techniques come at a cost in performance, the key design challenge continues… Driving Low-Power Design with High-Level Synthesis
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Digital Engineering Best Practices for Aerospace & Defense
Register for this Cadence TECHTALK™ webinar, where senior director of solutions marketing Frank Schirrmeister will discuss how commercial electronics hardware companies use cutting-edge design techniques to ensure that their hardware/software designs work as intended prior to fabrication. This ensures that hardware is built right the first time, in an affordable, sustainable, and agilely modernizable fashion.… Digital Engineering Best Practices for Aerospace & Defense
12 events found.