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Evaluating UCIe based multi-die architectures to meet timing and power constraints
Multi-die architectures have evolved from proprietary to industry standard UCIe. UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and… Evaluating UCIe based multi-die architectures to meet timing and power constraints
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ISTFA 2022
Pasadena Convention Center 300 East Green Stret, Pasadena, CA, United StatesThe demand for higher performance and lower power-consumption microelectronic devices has driven semiconductor technology to shrink continuously according to Moore’s Law. Furthermore, for latest technologies in nano realm, a new set of disruptive development in new structures and novel materials was introduced. Thus, defects causing semiconductor device failures have become smaller and more elusive. To… ISTFA 2022
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ICCAD 2022
San Diego Mission Bay Resor 1775 East Mission Bay Drive, San Diego, CA, United StatesJointly sponsored by ACM and IEEE, ICCAD is the premier forum to explore the new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. ICCAD covers the full range of CAD topics – from device and circuit-level up through system-level, as well as post-CMOS design. ICCAD has a long-standing tradition of producing a… ICCAD 2022
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CEDA Virtual Distinguished Lecturer Series: Anupam Chattopadhyay
The continued scaling of horizontal and vertical physical features of silicon-based complementary metal-oxide-semiconductor (CMOS) transistors, termed as “More Moore”, has a limited runway and would eventually be replaced with “Beyond CMOS” technologies. There has been a tremendous effort to follow Moore’s law but it is currently approaching atomistic and quantum mechanical physics boundaries. This has… CEDA Virtual Distinguished Lecturer Series: Anupam Chattopadhyay
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Linley Fall Processor Conference 2022
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesTechInsights is pleased to announce that the Linley Fall Processor Conference powered by TechInsights - a Hybrid Event, will be held in Santa Clara, California on November 1-2, 2022. If you cannot attend in person, tune in to our virtual livestream or watch the presentations OnDemand at your convenience. Presentations will address processors and IP… Linley Fall Processor Conference 2022
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Analog Design on the Cloud
Customers love the Synopsys Analog Design Solution and have been adopting it at a record pace. Now it's available on the cloud. Synopsys Cloud Analog Instance includes everything you need to get started quickly: software, hardware setup, training, and scripts to help setup and manage your design. Designers not only have access to a full… Analog Design on the Cloud
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How CXL Technology will Revolutionize the Data Center
Data Centers face many challenges in an environment of exponentially rising data volume growth. With workload demands increasing rapidly, the need for more bandwidth and capacity continues to rise. Join us for a live webinar next week on November 2nd and hear IDC guest speaker, Jeff Janukowicz, and Rambus' Mark Orthodoxou discuss how CXL technology… How CXL Technology will Revolutionize the Data Center
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THE FUTURE OF MORE THAN MOORE—Chiplets, Advanced Packaging, and More
Biamp Systems 9300 SW Gemini Dr., Beaverton, OR, United StatesPresented by the SEMI Pacific Northwest and Silicon Valley Chapters How can we extend Moore's Law and drive new capabilities in the More than Moore era? The answer lies in the technology, economics, and new opportunities in the semiconductor supply chain. Join us at the Forum on Thursday, November 3, 2022, 8–11:30am Pacific Time to… THE FUTURE OF MORE THAN MOORE—Chiplets, Advanced Packaging, and More
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Workshop on Open-Source EDA Technology
Virtually co-sponsored by ICCAD 2022 on November 3, 2022! The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that… Workshop on Open-Source EDA Technology
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How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
Join us on Thursday, November 3rd to learn how Lawrence Berkeley National Laboratory, Fermilab, and Brookhaven National Laboratory collaborated and designed a custom ASIC chip to run at extremely cold temperatures, so that it can detect neutrinos! Register Today! Here’s what you can learn: Why study neutrinos and how to detect them DUNE experiment –… How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
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TSMC 2022 EU OIP Ecosystem Forum
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies Latest 3DIC chip stacking and advanced packaging processes, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications Updated design solutions for specialty technologies enabling ultra-low voltage, analog migration,… TSMC 2022 EU OIP Ecosystem Forum
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Achieving Fast Turnaround Time of Functional ECOs with Synopsys Formality ECO
Functional ECOs (engineering change orders) are an important part of the design cycle, enabling design teams to respond quickly to frequent, unexpected, and last-minute register-transfer logic (RTL) functional changes. ECOs are unavoidable, however, they are necessary to fix functional verification bugs or to add critical new features, which enable designers to deliver products with minimal… Achieving Fast Turnaround Time of Functional ECOs with Synopsys Formality ECO
12 events found.