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Don’t Take the Risk, Formally Verify Your RISC-V Cores
Synopsys Webinar | Thursday, May 25, 2023 | 9:00 a.m. PT According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. In this… Don’t Take the Risk, Formally Verify Your RISC-V Cores
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SiFive Maximizes Compute Density With Its RISC-V Processor Cores
IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density - compute horsepower per mm2 and per mW (e.g SPECint2006/mm2) - has been a driving goal for SiFive’s portfolio of… SiFive Maximizes Compute Density With Its RISC-V Processor Cores
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STAC Summit
New York Marriott Marquis 1535 Broadway, New York City, NY, United StatesSTAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment.
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Advanced Testbench for a Simple DUT
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more… Advanced Testbench for a Simple DUT
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Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
Increasingly complex automotive systems are driving the need for new and powerful E/E architectures, and new technology is emerging that offers a significant computational increase compared to previous generation SoCs. To deliver next-generation, differentiated software solutions, model-based design (MBD) workflows must be deployed to handle this new level of complexity. Code generation solutions that optimize… Accelerate Software Innovation Through Target-Optimized Code Generation and Virtual Prototypes
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RISC-V Summit Europe
Barcelona Barcelona, SpainOn 5-9th June, in Barcelona, RISC-V Summit Europe brings together developers, architects, technical decision and policy makers from across European RISC-V ecosystem. Attendees from academia, research, SMEs, industry and open source communities will gather to exchange knowledge, ideas, technologies, and research shaping the future of RISC-V computing. The event will include a single track of… RISC-V Summit Europe
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Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Built on a SystemVerilog Real Number Modeling (RNM) foundation, Xcelium automates the signal integration of digital and RNM code to achieve digital simulation speeds for mixed-signal designs. This… Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
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Run Ansys HFSS in the Cloud with AWS to Boost Simulation
About This Webinar Engineers worldwide use Ansys HFSS software to design high-frequency, high-speed electronics found in communications systems, advanced driver assistance systems (ADAS), satellites, and internet-of-things (IoT) products. Ansys HFSS is a 3D electromagnetic (EM) simulation software for designing and simulating high-frequency electronic products such as antennas, antenna arrays, RF or microwave components, high-speed interconnects,… Run Ansys HFSS in the Cloud with AWS to Boost Simulation
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Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
Fueled by the recent adoption by leading smartphone brands, the UWB wireless technology is enjoying an explosive growth in market interest and applications. In automotive, UWB is already the de-facto choice for Digital Keys in the premium segment. The deployment of UWB anchor points in modern car creates a cost-effective platform for offering advanced in-cabin radar,… Driving Forward with UWB Radar: Enhancing Child Safety in Automotive
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PCI-SIG Developers Conference 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe PCI-SIG Developers Conference 2023 is returning to Santa Clara on June 13-14, 2023! Members of the PCI-SIG community including systems architects, designers, engineers, and engineering managers agree that this is an event you won’t want to miss. Overview The PCI-SIG Developers Conferences is a free event for our 900+ member companies that develop and bring… PCI-SIG Developers Conference 2023
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Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage of the project. The verification process starts from defining the verification goals,… Verify Your SoC Design Efficiently from Planning to Coverage Closure using Synopsys Verification Family
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Microelectronics Design Security: Better with Formal Methods
Whether you are developing Systems-on-Chip (SoCs) for mobile and wearables, automotive, aerospace, defense, data centers, or entertainment, securing your proprietary data and customers’ information is critical to your company’s long-term success. Hackers can exploit vulnerabilities in these systems — at the network, system, device, or chip levels. As SoC designs get more complex, this 30-minute… Microelectronics Design Security: Better with Formal Methods
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