-
3D & Systems Summit
Dresden Hilton Hotel An der Frauenkirche 5 D, Dresden, GermanyThe SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market, products, and tech advancements brought by disruptive technologies and Moore's Law plateauing. Therefore, continued developments and innovation are essential to growing the business. Industry experts will share their insights into… 3D & Systems Summit
-
SFF & SAFE™ Forum 2023 San Jose, CA
Signia by Hilton 170 S Market Street, San Jose, CA, United StatesDay 1 June 27th, 2023 12:00 - 1:00pm PDT Networking Lunch & Registration 1:00 - 1:05pm PDT Opening Jinman Han EVP, Head of DSA Office, Samsung Electronics 1:05 - 1:20pm PDT Samsung Keynote Siyoung Choi President and GM, Foundry Business, Samsung Electronics 1:20 - 1:35pm PDT An Energy Efficient Future of AI Joe Macri SVP, CTO… SFF & SAFE™ Forum 2023 San Jose, CA
-
2023 Andes RISC-V CON
The DoubleTree by Hilton 2050 Gateway Place, San Jose, CA, United StatesRISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility.… 2023 Andes RISC-V CON
-
Verisium Debug for UPF Low Power Design
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. What you… Verisium Debug for UPF Low Power Design
-
30th MIXDES Conference
Lodz Univesity of Technology Wólczańska 221/223, Lodz, PolandThe aim of the MIXDES conference is to provide an annual Central-European forum for the presentation and discussion of recent advances in design, modeling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices. The MIXDES conference papers will be submitted for inclusion into IEEE Xplore, subject… 30th MIXDES Conference
-
UCIe PHY Modeling and Simulation with XMODEL
Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital… UCIe PHY Modeling and Simulation with XMODEL
-
TSMC 2023 Technology Symposium – Japan
The Yokohama Bay Hotel Tokyu 2-3-7, Minatomirai, Nishi-ku, Yokohama, JapanJapan Technology Symposium Date Friday, June 30 Time 9:30 a.m. - 5:20 p.m. Venue The Yokohama Bay Hotel Tokyu 2-3-7, Minatomirai, Nishi-ku, Yokohama 220-8543 Registration will be closed on 6/21. Seats are limited. VoD (Video on Demand) will be available starting from 7/21. Registration will close on 7/12. Get the latest on: TSMC's smartphone, HPC,… TSMC 2023 Technology Symposium – Japan
-
FPGA Conference Europe 2023
NH München Ost Conference Center Einsteinring 20, Munich, Aschheim, GermanyFPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is addressing that progress across all major manufacturers. It focusses on user-oriented, practically applicable solutions that developers can quickly integrate into… FPGA Conference Europe 2023
-
Free Silicon Conference – FSiC2023
Sorbonne Université 15-21 Rue de l'École de Médecine, Paris, FranceThe 2023 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 10,11,12 2023 (Monday to Wednesday). This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will… Free Silicon Conference – FSiC2023
-
Embedded UVM (eUVM)
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 11th July with a theme of "Embedded UVM(eUVM)". Introduction to Embedded UVM to enable HPC-Powered UVM Testbenches with MultiCore Performance. Agenda (BST) 12:00 Welcome and Introduction - Mike Bartley, Senior Vice President - VLSI Design, Tessolve 12:00 Puneet Goel, Coverify Systems Technology LLP… Embedded UVM (eUVM)
-
An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the "right set" of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution space and lowering the required tool expertise. This CadenceTECHTALK™ presents details on… An AI/ML Driven High-Level Synthesis Solution
-
Comprehensive Static Verification for FPGA and ASIC RTL Designers
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source. This webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for… Comprehensive Static Verification for FPGA and ASIC RTL Designers
12 events found.