Calendar of Events
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2 events,
European Nanoelectronics Applications Design and Technology Conference
FOCUS The European Nanoelectronics Applications, Design & Technology Conference will focus on electronic components, electronic system design, design automation, and manufacturing topics related to micro- and nanoelectronics, which are critical to success for many European companies. Exhaustive research and development in this area have been supported by EUREKA, Horizon Europe, and local governments in recent… Read More »European Nanoelectronics Applications Design and Technology Conference
3D & Systems Summit
The SEMI 3D & Systems Summit this year is dedicated to Smarter Systems through Heterogeneous Integration. The semiconductor industry has had several changes in market, products, and tech advancements brought by disruptive technologies and Moore's Law plateauing. Therefore, continued developments and innovation are essential to growing the business. Industry experts will share their insights into… Read More »3D & Systems Summit
5 events,
SFF & SAFE™ Forum 2023 San Jose, CA
Day 1 June 27th, 2023 12:00 - 1:00pm PDT Networking Lunch & Registration 1:00 - 1:05pm PDT Opening Jinman Han EVP, Head of DSA Office, Samsung Electronics 1:05 - 1:20pm PDT Samsung Keynote Siyoung Choi President and GM, Foundry Business, Samsung Electronics 1:20 - 1:35pm PDT An Energy Efficient Future of AI Joe Macri SVP, CTO… Read More »SFF & SAFE™ Forum 2023 San Jose, CA
2023 Andes RISC-V CON
2023 Andes RISC-V CON
RISC-V is revolutionizing the future of Artificial Intelligence (AI) in industries such as automotive, data center, communications, and IoT. Its open-source instruction set architecture (ISA) provides higher performance, lower power, and compact silicon footprint, features highly desired by these industry segments. RISC-V has gained rapid widespread adoption due to its compact instruction set and extensibility.… Read More »2023 Andes RISC-V CON
Verisium Debug for UPF Low Power Design
Verisium Debug for UPF Low Power Design
Verisium Debug offers comprehensive debugging capabilities. From RTL, UVM testbench to UPF low-power designs, users can use the Cadence unified debugging platform for debugging. In this webinar, users will learn about the available features in Verisium Debug for UPF power-aware designs and using the unique capabilities to visualize and debug UPF low-power designs. What you… Read More »Verisium Debug for UPF Low Power Design
2 events,
30th MIXDES Conference
The aim of the MIXDES conference is to provide an annual Central-European forum for the presentation and discussion of recent advances in design, modeling, simulation, testing and manufacturing in various areas such as micro- and nanoelectronics, semiconductors, sensors, actuators and power devices. The MIXDES conference papers will be submitted for inclusion into IEEE Xplore, subject… Read More »30th MIXDES Conference
UCIe PHY Modeling and Simulation with XMODEL
UCIe PHY Modeling and Simulation with XMODEL
Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital… Read More »UCIe PHY Modeling and Simulation with XMODEL
2 events,
TSMC 2023 Technology Symposium – Japan
TSMC 2023 Technology Symposium – Japan
Japan Technology Symposium Date Friday, June 30 Time 9:30 a.m. - 5:20 p.m. Venue The Yokohama Bay Hotel Tokyu 2-3-7, Minatomirai, Nishi-ku, Yokohama 220-8543 Registration will be closed on 6/21. Seats are limited. VoD (Video on Demand) will be available starting from 7/21. Registration will close on 7/12. Get the latest on: TSMC's smartphone, HPC,… Read More »TSMC 2023 Technology Symposium – Japan
1 event,
FPGA Conference Europe 2023
FPGAs have made a regular evolutional leap forward in terms of new approaches and solutions for both hardware- and software developers. The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is addressing that progress across all major manufacturers. It focusses on user-oriented, practically applicable solutions that developers can quickly integrate into… Read More »FPGA Conference Europe 2023
1 event,
Free Silicon Conference – FSiC2023
The 2023 Free Silicon Conference (FSiC) will take place in Paris (Sorbonne) on July 10,11,12 2023 (Monday to Wednesday). This event will build on top of the past FSiC2019 and FSiC2022 editions. The conference will connect experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference will… Read More »Free Silicon Conference – FSiC2023
2 events,
Embedded UVM (eUVM)
Embedded UVM (eUVM)
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 11th July with a theme of "Embedded UVM(eUVM)". Introduction to Embedded UVM to enable HPC-Powered UVM Testbenches with MultiCore Performance. Agenda (BST) 12:00 Welcome and Introduction - Mike Bartley, Senior Vice President - VLSI Design, Tessolve 12:00 Puneet Goel, Coverify Systems Technology LLP… Read More »Embedded UVM (eUVM)
2 events,
An AI/ML Driven High-Level Synthesis Solution
An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the "right set" of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution space and lowering the required tool expertise. This CadenceTECHTALK™ presents details on… Read More »An AI/ML Driven High-Level Synthesis Solution
1 event,
Comprehensive Static Verification for FPGA and ASIC RTL Designers
Comprehensive Static Verification for FPGA and ASIC RTL Designers
As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source. This webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for… Read More »Comprehensive Static Verification for FPGA and ASIC RTL Designers
3 events,
Rambus Design Summit 2023
Back for its fourth year, the Rambus Design Summit is a virtual conference focused on the key technologies critical to enabling performance and security for data center, AI/ML, automotive and IoT applications. Agenda + Abstracts Rambus Design Summit will take place over two days, with day one focusing on memory & interface solutions, and day… Read More »Rambus Design Summit 2023
Key MAC Considerations for the Road to 1.6T Ethernet Success
Key MAC Considerations for the Road to 1.6T Ethernet Success
224G SerDes designs are a reality and the path to 1.6T is clearer than ever. This webinar delves into the considerations, challenges and solutions designers need to know for the MAC required for these 224G Ethernet PHY IP designs. Dive deep into the nuances of PHY/MAC layer interactions, timing considerations, and forward error correction. We will… Read More »Key MAC Considerations for the Road to 1.6T Ethernet Success
Automated Verification for Cache Coherent RISC-V SoCs
Automated Verification for Cache Coherent RISC-V SoCs
RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches. In this webinar, we’ll demonstrate how Perspec System Verifier, with the pre-defined System Traffic Library (STL), provides an out-of-the-box verification plan and test suite… Read More »Automated Verification for Cache Coherent RISC-V SoCs
2 events,
Achieve Optimal PPA Targets Using AI-Driven Technology
Achieve Optimal PPA Targets Using AI-Driven Technology
Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power, performance, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing, and traditional methods cannot keep pace often taking months of tuning using 100s of… Read More »Achieve Optimal PPA Targets Using AI-Driven Technology
2 events,
3D-IC Foundry Frameworks
3D-IC Foundry Frameworks
Join us on July 20th; Ansys R&D members will discuss an overview of the 3D-IC technology development frameworks offered by TSMC, Samsung, and Intel and how Ansys simulation tools and workflows fit into those frameworks. About this Webinar Semiconductor applications such as Mobile (5G), Automotive, and Datacenter (HPC, AI) demand better scaling, performance, and lower… Read More »3D-IC Foundry Frameworks
Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc., correctness of constraints requires the same level of attention. Quality of implementation and timing analysis is highly dependent on quality of constraints. For achieving first-past… Read More »Achieve First-pass Silicon Leveraging SDC Verification Early with No Noise
2 events,
ITC India 2023
Keynote speakers Fadi Maamari VP of Engineering at Synopsys Sule Ozev Arizona State University About Us International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back… Read More »ITC India 2023
International Test Conference – India, 2023
International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC India, design, test, and yield professionals can confront challenges… Read More »International Test Conference – India, 2023
3 events,
Solution for 3D-IC Interposer Signal Integrity
Solution for 3D-IC Interposer Signal Integrity
3D-IC design requires early analysis of thermal properties, power delivery, and signal integrity. This webinar will work through the process of simulating heterogeneously integrated chiplets. Learn about the integrated workflow that begins with silicon design data being accurately modeled with 3D FEM extraction. The Cadence Clarity 3D Solver has the unique ability to efficiently import… Read More »Solution for 3D-IC Interposer Signal Integrity
Solution for 3D-IC Interposer Signal Integrity
Solution for 3D-IC Interposer Signal Integrity
Our upcoming CadenceTECHTALK: Solution for 3D-IC Interposer Signal Integrity is designed to teach engineers to translate a GDSII stream format (GDSII) file and partition it into simulation blocks for the Clarity 3D field solver. First, you will learn to use GDS-supporting files to simplify GDS to SPD translation and reuse those files to make the… Read More »Solution for 3D-IC Interposer Signal Integrity
A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. Synopsys Formality ECO offers an efficient and accurate solution for RTL ECO… Read More »A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
1 event,
EMC+SIPI 2023
EMC+SIPI 2023 leads the industry in providing state-of-the-art education on EMC and Signal Integrity and Power Integrity techniques. Don't miss out on this valuable opportunity to learn from and network with industry leaders and peers.
2 events,
Accelerate Coverage Closure with Synopsys VSO.ai
Accelerate Coverage Closure with Synopsys VSO.ai
70% of engineering time is spent verifying a design but it is largely a manual effort. As the industry faces ongoing engineering shortages companies are forced to make their engineering teams 10 times more productive at finding and isolating bugs per day. Increasing design complexities are also driving up the compute resources needed to verify… Read More »Accelerate Coverage Closure with Synopsys VSO.ai
2 events,
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single "executable" specification. Appropriate Audience: ● Architects/RTL Designers ● Verification Engineers ● Pre-Silicon Validation Teams ● Post-Silicon Lab Bring-up Team Members ● Technical Writers ● Firmware Engineers ● Embedded Programmers Learn… Read More »An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development