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Cadence Training: Cerebrus Intelligent Chip Explorer
Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar. What Is the Webinar About? The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow… Cadence Training: Cerebrus Intelligent Chip Explorer
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Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. This CadenceTECHTALK introduces a novel High-Level… Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
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FPGA Design Verification – Advanced Testbench Implementation
Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification… FPGA Design Verification – Advanced Testbench Implementation
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56th International Microelectronics Assembly and Packaging Society (IMAPS)
This packed conference brings together industry engineers, researchers and top experts involved in advanced packaging and microelectronics assembly. IMAPS Symposium offers a robust technical program with 5 concurrent tracks and 100+ speakers and posters covering SiP Design / Manufacturing Optimization; Wafer Level / Panel Level (Advanced RDL); High Performance, High Reliability; Advanced Packages (Flip Chip, 2.5D,… 56th International Microelectronics Assembly and Packaging Society (IMAPS)
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TSMC 2023 Europe OIP Ecosystem Forum
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… TSMC 2023 Europe OIP Ecosystem Forum
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Verisium Debug for UVM Testbench
Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. What you will learn Understand… Verisium Debug for UVM Testbench
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EDPS 2023
Synopsys Building 1 800 North Mary Avenue, Sunnyvale, CA, United StatesEDPS 2023 is approaching fast! The program is firming up - please see the program page for a preliminary list of talks. REGISTRATION IS NOW OPEN. Everyone, including speakers, must register. 2023-ieee-edps.eventbrite.com Note that this year we'll be meeting on the Synopsys Campus. Synopsys Building 1 800 North Mary Avenue Sunnyvale, CA, 94085 Most of the talks… EDPS 2023
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FPGA Design Verification – Advanced Methods
Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification… FPGA Design Verification – Advanced Methods
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CadenceLIVE Europe 2023
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyCadenceLIVE Europe 2023 – experience the power of intelligent system design - brings together users, developers, and industry experts to network, share ideas, and inspire design innovation in the most complex electronics and intelligent systems. The event features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. Attendees will be able to… CadenceLIVE Europe 2023
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Synopsys Verification Technical Symposium 2023 – Israel
Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, IsraelJoin us for a day filled with insights, innovation, and networking in the semiconductor industry. The verification landscape is evolving, and we're here to help you navigate it. At this symposium, we’ll be going through some of the most challenging use cases in chip design today, while exploring best practices and the latest innovations for… Synopsys Verification Technical Symposium 2023 – Israel
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Keysight EDA 2024
Shift Left to Raise Design Productivity We're ready to demo the latest release of our suite of electronic design automation (EDA) software tools so that you can learn how to increase productivity by shifting left your design process and product development cycles. Four Tracks to Choose from We'll kick off each session with an overview… Keysight EDA 2024
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Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA. Key Takeaways: Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more. Understand latency… Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
12 events found.