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Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints
October 11 @ 9:00 am - 10:00 am PDT
In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.
- Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more.
- Understand latency and throughput trade-offs when using NoC vs. direct interfaces.
- Learn how different data cache sizes impact AIE Tile network utilization.
- Dive into various mapping decisions and their effect on application throughput and power consumption.
So, what are you waiting for? Don’t miss this opportunity