Workshop on the Evolution of SystemC Standards
The SystemC Evolution Fika is a series of online workshops to discuss the latest SystemC developments and applications. We refer to these workshops as fikas, to honor the fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about. Event information Date: 15 September 2022 Time: 16:00 - 18:00 CEST Location:… Read More »Workshop on the Evolution of SystemC Standards
ESSCIRC 2022
Università degli Studi di MILANO - BICOCCA Viale Piero e Alberto Pirelli, 22, Milano, ItalyThe aim of ESSDERC and ESSCIRC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on- chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC… Read More »ESSCIRC 2022
SNUG Israel 2022
Daniel Herzliya Hotel Ramat Yam St 60, Herzliya, IsraelSince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users around the world. In addition to peer-reviewed technical presentations and insightful keynotes from industry leaders, SNUG provides… Read More »SNUG Israel 2022
MIPI DevCon 2022
MIPI DevCon 2022 will be held 20-21 September, offering developers and implementers of MIPI specifications a forum for training, education and networking. The virtual event will feature conference presentations by MIPI experts and working group leaders sharing use cases, implementation experiences and application examples – all from a technical perspective. Open to all Alliance members and… Read More »MIPI DevCon 2022
Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are of little value if they cannot be verified through Formal Equivalence Verification (FEV). FEV setup must be… Read More »Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming more… Read More »Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Xcelium Apps: Everything You Need in the Simulation Metaverse
Register for this CadenceTECHTALK if you are looking for an end-to-end solution for all your verification requirements in automotive, mobile, and hyperscale designs. This CadenceTECHTALK introduces Xcelium Apps, a portfolio of domain-specific technologies implemented natively on the Cadence Xcelium Logic Simulator. The Xcelium Apps are a paradigm shift in the way verification is being done,… Read More »Xcelium Apps: Everything You Need in the Simulation Metaverse
Victory Visual, Silvaco’s New Graphical Visualization Solution for TCAD
Victory Visual is a new graphical post processing tool for use with all Silvaco TCAD simulators. It is an integral part of the TCAD Interactive Tools suite. Victory Visual can operate standalone or along with other Silvaco TCAD tools, such as DeckBuild. While users of TonyPlot or TonyPlot3D will find some of the functionality familiar,… Read More »Victory Visual, Silvaco’s New Graphical Visualization Solution for TCAD
From MATLAB to Optimized RTL in Minutes
As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. To mitigate this challenge, Cadence and MathWorks have collaborated to… Read More »From MATLAB to Optimized RTL in Minutes
The Keys to SystemC & TLM-2.0: How to be Successful
SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference models in the hardware verification flow. This session is aimed at hands-on hardware or software engineers who might know Verilog… Read More »The Keys to SystemC & TLM-2.0: How to be Successful
Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
The West Anaheim Resort 1030 West Katella Avenue, Anaheim, CA, United StatesAs a member of the design and test community, you are invited to attend Synopsys 28th Annual Test & SLM Special Interest Group (SIG) at the 2022 International Test Conference (ITC). This year’s event will be hosted by Dr. Ken Butler, Senior Director of Business Development from Advantest. Dr. Butler will be joined by experts… Read More »Synopsys 28th Annual Test & SLM Special Interest Group (SIG) Event
U.S. Executive Forum
The 2022 GSA U.S. Executive Forum is coming up on September 27 in Menlo Park, California. USEF 2022 is one of the most anticipated GSA events of the year and attendance is filling up quickly. Make sure to secure your spot before it's too late. In this unique and exclusive gathering, thought leaders, visionaries and innovators… Read More »U.S. Executive Forum