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Analog Layout with Thomas Parry and Tim Edwards
In this webinar we will take the comparator circuit from last time and look at how to do the layout with the 2 most used open source layout tools. We will send the link to the webinar recording to those who registered. We will cover: Creation of the transistors Layout with Magic Layout with Klayout… Analog Layout with Thomas Parry and Tim Edwards
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The Power of Verilog’s PLI and VPI for FPGA Designs
A logic simulator’s programming interfaces can be used for not only verifying logic IP but also the co-development of logic and embedded software. Our ‘Introducing Logic Simulator Programming Interfaces for FPGA designs’ three-part webinar series starts on April 13. Our guest presenter for this series is Simon Southwell, from Anita Simulators, and the schedule is… The Power of Verilog’s PLI and VPI for FPGA Designs
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ASIC Design Using OpenROAD
UCSC Silicon Valley Extension 3175 Bowers Ave, Santa Clara, CA, United StatesJoin us for a free, half-day workshop on the key concepts of an ASIC design physical implementation flow using OpenROAD. OpenROAD delivers a fast, barrier-free, and low-cost RTL-to-GDS, no-human-in-loop flow for design above 12nm and is one of the tools students can work with in UCSC Silicon Valley Extension VLSI Engineering program courses Knowing how to use open EDA tools boosts… ASIC Design Using OpenROAD
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DATE 2023
Flanders Meeting & Convention Center Antwerp Antwerp, BelgiumThe DATE conference is the main European event bringing together designers and design automation users, researchers and vendors as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well… DATE 2023
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Hannover Messe 2023
Hannover Expo-Plaza Hannover, GermanyExhibitors & Products Conference Program Networking AI & Machine Learning Carbon-neutral production Energy Management Hydrogen & Fuel Cells Industry 4.0
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3rd Workshop on Open-Source Design Automation
Flanders Meeting & Convention Center Antwerp Antwerp, BelgiumCall for papers There is no doubt that proprietary EDA tools are successful, mature, and fundamental for hardware development. However, the “walled garden” approach created by closed-source tool flows can hamper novel FPGA/ASIC-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require… 3rd Workshop on Open-Source Design Automation
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CS International Conference
Sheraton Brussels Airport Hotel Brussels, Belgiumhe 13th CS International conference builds on the strengths of its predecessors, with around 40 leaders from industry and academia delivering presentations that fall within five key themes: Ultrafast Communication; Making Headway with the MicroLED; Taking the Power from Silicon, New Vectors for the VCSEL, and Ultra-wide Bandgap Devices. Delegates attending these sessions will gain… CS International Conference
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Static Sign-Off Symposium 2023
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesAdvanced Static Sign-Off Methodologies Leading SoC designers will share their advanced static sign-off methodologies and best practices to support first-silicon design goals, along with results achieved in accelerating early functional verification and sign-off of digital designs. Topics will include: AI/ML, targeted sign-off, incremental sign-off, multimode, hierarchical, dynamic CDC, and more. Advanced Static Sign-Off Methodology Presenters:… Static Sign-Off Symposium 2023
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CadenceLIVE Silicon Valley 2023
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesJoin us for CadenceLIVE™ Silicon Valley 2023, held on April 19-20 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products. CadenceLIVE brings together users, developers, and industry experts to connect, share ideas, and inspire design creativity. Attendees have the… CadenceLIVE Silicon Valley 2023
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Taking the Risk out of RISC-V with Fast, Architecture-Driven, PPA Optimization
The use of the RISC-V ISA to develop processors for SoCs is a growing trend. An important driver is the ability to customize or create ISA and micro-architectural extensions to differentiate designs across application areas including AI, machine learning, automotive, data center, mobile, and consumer. Traditionally, designing proprietary cores with the right extensions has been… Taking the Risk out of RISC-V with Fast, Architecture-Driven, PPA Optimization
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CICC 2023
Sponsored by IEEE and SSCS, the IEEE Custom Integrated Circuits Conference – CICC – is a premier conference devoted to IC development. The conference program is a blend of oral presentations, exhibits, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference… CICC 2023
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D&R IP-SoC Silicon Valley 2023
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesWhere : Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services… D&R IP-SoC Silicon Valley 2023
12 events found.