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  • Keysight EDA 2024

    Shift Left to Raise Design Productivity We're ready to demo the latest release of our suite of electronic design automation (EDA) software tools so that you can learn how to increase productivity by shifting left your design process and product development cycles. Four Tracks to Choose from We'll kick off each session with an overview… Keysight EDA 2024

  • Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints

    In this Webinar, we will focus on the performance-power-area trade-off in implementing signal processing algorithms on Xilinx FPGA by partitioning the tasks of the algorithms onto the processors, logic and AI Engines resident in the AMD-Xilinx Versal FPGA.  Key Takeaways: Discover the inner workings of FPGA components: Processor, Logic Elements, AIE/Tensor, and more. Understand latency… Mapping signal processing algorithms on AMD-Xilinx Versal to meet timing and power constraints

  • Synopsys Technology Symposium UK 2023

    Reading FC Conference Centre Reading RG2 0FL, Berkshire, United Kingdom

    Synopsys is hosting a Technical Symposium focusing on critical aspects of doing state of the art designs at established and emerging nodes. This event provides an opportunity for users to stay connected with the latest innovations as well as getting tips & tricks and best practices that fellow users and Synopsys experts will share. Multiple… Synopsys Technology Symposium UK 2023

  • Proactively Address Thermal Concerns in Advanced IC Packages

    The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. This webinar will show how design… Proactively Address Thermal Concerns in Advanced IC Packages

  • The UCIe™ 1.1 Specification: Future Applications of Chiplets

    Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel  The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide… The UCIe™ 1.1 Specification: Future Applications of Chiplets

  • IEEE 32nd Asian Test Symposium

    With the test technology facing its grand challenges to ensure the quality of ICs and electronic systems, incorporating more and more sophisticated manufacturing processes and system integration technologies in various emerging applications such as Internet of Things, cloud computing, automotive electronics, etc., global proliferation and cooperation is increasingly more important. The Asian Test Symposium (ATS)… IEEE 32nd Asian Test Symposium

  • EPEPS 2023

    Sonesta San Jose - Milpitas 777 Bellew Drive, Milpitas, CA, United States

    EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Electronics Packaging Society, IEEE Microwave… EPEPS 2023

  • DVClub Europe – AI/ML in Verification

    This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of "AI/ML in Verification". This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Agenda (BST) 12:00   Welcome and Introduction - Mike Bartley, Senior Vice President -… DVClub Europe – AI/ML in Verification

  • Samsung Foundry Forum 2023 Tokyo, Japan

    Belle Salle Tokyo Nihonbashi 2-7-1 Nihombashi, Chuo-ku, Tokyo, Japan

    Welcoming Remarks Seishu Arai VP, Head of Japan Office, Samsung Electronics Samsung Keynote Siyoung Choi President and GM, Foundry Business, Samsung Electronics Guest Speech I Junichiro Makino Professor, Kobe University Guest Speech II Sumiko Kanamori Automotive HPC, Analog & Power Solutions Gr. Digital Head of H/W Unit, VP, Renesas Electronics Corporation Guest Speech III Kazuoki… Samsung Foundry Forum 2023 Tokyo, Japan

  • Jasper User Group 2023

    Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual CadenceCONNECT: Jasper™ User Group Conference, held on October 18 and 19 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around… Jasper User Group 2023

  • Soar to New Heights of Productivity using Cadence Managed Cloud Services

    Date: Wednesday, October 18, 2023 Time: 8:30am PT | 10:30am CT | 11:30am ET Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design, verification, and implementation. See the platform in action as we demo the productivity features… Soar to New Heights of Productivity using Cadence Managed Cloud Services

  • The Race is On!

    Brazos Hall East 4th Street, Austin, TX, United States

    Event Overview Date: Wednesday, October 18, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Brazos Hall, Austin, TX There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design. The… The Race is On!