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Efficient Design Methodology for 112G Interface Compliance
As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and… Efficient Design Methodology for 112G Interface Compliance
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What’s New About Virtuoso Layout Suite?
Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio How can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR)… What’s New About Virtuoso Layout Suite?
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GSA International Semiconductor Conference
Here East 14 E Bay Lane, London, United KingdomInaugural GSA event in partnership with the UK Government. Meet senior business leaders, investors, and public policy officials from around the world. Across two days, join us for exciting discussions… GSA International Semiconductor Conference
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New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of… New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
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GOMACTech 2024
Embassy Suites by Hilton Charleston Convention Center, Charleston, SC, United StatesGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of… GOMACTech 2024
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Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However, many of you have realized that the lack of completeness of rules in the techfile… Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
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DVClub Europe: Latest VHDL Verification Techniques
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic - Get the… DVClub Europe: Latest VHDL Verification Techniques
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SNUG Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesConnecting the Synopsys User Community SNUG conferences have connected Synopsys global users for more than three decades. SNUG 2024 will once again provide a place where users and technical experts… SNUG Silicon Valley 2024
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Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
With the growing complexities of 3D-ICs, chiplets, advanced packaging, and high-performance boards, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before… Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
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AI-Powered Electromagnetics Symposium
Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United StatesAccelerate Your Designs with Generative AI-Powered Multiphysics Analysis and Optimization How are you addressing the ever-increasing complexity and density of your high-performance electronic systems? What role do electromagnetic effects such… AI-Powered Electromagnetics Symposium
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High-Performance RTL Simulation Workflow with Vivado and Active-HDL
Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032.… High-Performance RTL Simulation Workflow with Vivado and Active-HDL
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Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can… Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
12 events found.