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PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
“Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into the layout that cause issues during lab testing and result in costly, time-consuming respins. Join our expert presenter Todd Westerhoff in this LinkedIn Live… PCB Design Best Practices: How to fully verify your Serdes-based designs before prototype manufacture
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Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones. One way to improve efficiency is to shift signal and power integrity (SI/PI) analysis to earlier in… Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
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ASP-DAC 2024
Incheon Songdo Convensia 123 Central Street, Yeonsu-gu, Incheon, Korea, Democratic People's Republic ofASP-DAC 2024 is the 29th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design, CAD and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances… ASP-DAC 2024
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Verisium SimAI: Coverage Gaps Meet Their Match
Every project has some areas that seem impossible to cover. Various factors can cause these nearly impossible-to-hit coverage gaps, including technical complexity, lack of resources, and shifting requirements. In constrained random environments, simply running more random seeds may not always address these coverage gaps effectively. Overcoming these gaps requires creativity, persistence, and technical expertise. A… Verisium SimAI: Coverage Gaps Meet Their Match
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Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
Applications such as Data Centers, High-Performance computing (HPC), artificial intelligence/machine learning (AI/ML), cloud computing, military, and aerospace, automotive, etc. are all extremely Bandwidth-hungry. To cater to such high demands of high speeds and bandwidth requires a breakthrough that HPC SoCs are constantly facing. High speed interfaces like PCI Express® (PCIe®) 5.0 and 6.0 show promising… Comprehensive PCIe Verification Solution for bleeding edge and mission critical SoC & IP Designs
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Automotive World 2024
Tokyo Big Sight 3 Choe-11-1 Ariake, Tokyo, JapanCombination of exhibitions & conferences covering important topics in the automotive industry such as automotive electronics, connected car, autonomous driving, EV/HV/FCV, lightweight, processing technology and MaaS. Automotive OEMs and Tier 1 suppliers visit the exhibition to find suppliers and partners. 1,650 Exhibitors 85,000 Visitors 170 Speakers
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Introducing OrCAD X, Our Next-Generation PCB Layout Solution
Whether you’re a beginner or a seasoned engineer, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment. Learn how you can: Design with an intuitive UI Collaborate using design review and markup… Introducing OrCAD X, Our Next-Generation PCB Layout Solution
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Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
Join us for an engaging webinar as we delve into the boundless possibilities of RISC-V architecture with a focus on the comprehensive Total Solutions offered by the Andes Series. Explore how these cutting-edge RISC-V CPU cores are reshaping the landscape of computing, powering innovations across diverse applications such as automotive and AI. Our experts will… Releasing All Potential of RISC-V: Total Solutions of Andes Core Processors Series
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Validating Clarity 3D Solver Accuracy Through Measurement Correlation
Cadence’s Clarity 3D Solver is an industry-leading EM simulation platform used by hundreds of design teams to address signal and power integrity (SI/PI) challenges. By solving bigger problems on more efficient compute resources, Clarity 3D Solver users have reimagined what can be done with 3D finite element method (FEM) solver technology. However, EM extraction results to… Validating Clarity 3D Solver Accuracy Through Measurement Correlation
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Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects, Aldec provides FPGA vendor-agnostic AXI Bus… Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
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DesignCon 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe Must Attend Event for Chip, Board, and Systems Design Engineers DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. 40 Under 40 Calling all Emerging Engineers and Leaders! DesignCon’s 40 Under 40 program launches in 2024 and provides… DesignCon 2024
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Signal & Power Integrity Special Interest Group
Hilton Santa Clara 4949 Great America Parkway, Santa Clara, CA, United StatesDear SIPI Engineer, As a member of the engineering community, you are invited to attend Synopsys Signal & Power Integrity Special Interest Group event taking place at Hilton Santa Clara. This event is conveniently located across the street from the DesignCon 2024 Conference allowing you to participate in both. The Synopsys SIPI SIG event will… Signal & Power Integrity Special Interest Group
12 events found.