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Fostering a Photonics Ecosystem for Sustainable Adoption
Integrated photonics adoption has made tremendous progress but is still slow and uneven outside of its most common use in data communications. What will it take for photonics to become a “standard” technology in the toolbox of system designers? Join Cadence for the sixth-annual CadenceCONNECT Photonics event on December 7 – 9 to find out… Fostering a Photonics Ecosystem for Sustainable Adoption
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SEMICON West
Moscone Center 747 Howard Street, San Francisco, CA, United StatesYour Health & Safety is our first priority— Proof of Vaccination is REQUIRED to Attend SEMICON WEST IN-PERSON SEMICON West 2021 HYBRID IN-PERSON Dec 7–9 | Moscone Center, SF, CA Virtual | Online 24/7 SEMICON West is THE place to reconnect with colleagues, partners, customers, and find new connections to drive your business forward. It’s where the entire extended electronics supply chain… SEMICON West
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Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
Presented by Todd Westerhoff, Product Marketing Manager for High-Speed System Design, Siemens EDA Abstract The PCB layout team has just handed you back a routed database with hundreds of serial links routed to your specifications — now what? How can you validate every link-as-routed for protocol compliance before releasing the design? If you're like most… Ensuring Standards Compliance: Automating Post-Route Analysis for Hundreds of Serial Links
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PCIe 6.0 From IP to Interconnect in High-Performance Computing
ABSTRACT: PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density. System architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions. In… PCIe 6.0 From IP to Interconnect in High-Performance Computing
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Bug Tracking with Indago Interactive for Specman
Join Cadence® Training and Principal Application Engineer Daniel Bayer for this free technical training webinar. The Indago™ Debug Platform is optimized for scalability, supporting debug of simulation runs as well as emulation, where support for loading large source files and handling huge amounts of probe data is a must. Join this free Cadence Training Webinar… Bug Tracking with Indago Interactive for Specman
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2021 GSA Awards Celebration
GSA recognizes semiconductor companies that have demonstrated excellence through their success, vision, strategy and future opportunities in the industry at its annual Awards Celebration.
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67th IEEE IEDM
Hilton San Francisco Union Square 333 O'Farrell Street, San Francisco, United StatesIEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for… 67th IEEE IEDM
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DVCON India
This conference will give you ample opportunities to share and highlight your technical contibutions in the areas of Verificaiton and Validations, Methodology & Automation, Functional Safety & Security, Low Power and Mixed Signal Design, Static and Formal methods and Digital Twins and SystemC Modeling. Kindly use this opportunity and register yourself for the conference.… DVCON India
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Methodics User Group
Join our monthly session with Methodics IPLM experts and other users for open discussion, Q&A, and product demos. Next Session: December 14 | 1:00 P.M. EST Each 45-minute session offers a new opportunity to: Learn/share best practices. Interact with and learn from other users. Have Q&A time with our product experts on usage and methodology.… Methodics User Group
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SEMICON Japan
This year SEMICON Japan will be a hybrid event, providing a best-in-class platform for industry visionaries and partners to examine the latest advancement and challenges across AI, 5G, IoT, MEMS and Sensors, quantum computing, advanced 3D packaging, and more.
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Design and Analysis Solutions for Integrated RF Systems
Opening Keynote 10:00am EST | Cadence Solutions for RF Design Excellence, presented by David Vye, Dr. Melika Roshandell, Graeme Richie, Dr. Yashwanth Reddy Padooru, Gus Dallman, Shane Coffman, Cadence Technical Talks 11:00am EST | Design of Integrated Phased-Array Antenna Systems for 5G CPE, presented by David Vye, Andy Hughes, Cadence 1:00pm EST | Simulation and… Design and Analysis Solutions for Integrated RF Systems
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How to Overcome the Pain Points of AI/ML Hardware Design
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip data movement. Next-generation FPGA technology includes a 2D network on chip, GDDR6 memory interfaces and high performance machine learning processors, which present new capabilities to… How to Overcome the Pain Points of AI/ML Hardware Design
12 events found.