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PCIe 6.0 From IP to Interconnect in High-Performance Computing

December 8, 2021 @ 10:00 am - 11:00 am PST

synopsys, december 8, 2021


PCI Express (PCIe) is one of the most popular interface technologies in the world. Interconnects for high-performance computing (HPC) in the data center, cloud and AI edge continue to increase in speed and density. System architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge solutions.

In this webinar, technical experts from Synopsys and Samtec will discuss the latest developments in next-generation PCIe 6.0 solutions and demonstrate interoperable technology from IP to interconnect in HPC. Additionally, practical signal channel design techniques and connectivity options will be highlighted.


Madhumita Sanyal

Synopsys, Sr. Staff Technical Marketing Manager Madhumita Sanyal is a Senior Staff Technical Marketing Manager for Synopsys’ high-speed SerDes PHY IP portfolio. She has over 16 years of experience in design and application of ASIC WLAN products, logic libraries, embedded memories, and mixed-signal IP. Madhumita holds a Master of Science degree in Electrical Engineering from San Jose State University and LEAD from Stanford Graduate School of Business.

Matthew Burns

Samtec, Technical Marketing Manager Matthew Burns develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years, he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University. *This webinar is in partnership with SemiWiki, Samtec, and Synopsys


December 8, 2021
10:00 am - 11:00 am PST
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