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Keeping Latency to a Minimum with 400G/800G Ethernet IP
A large volume of data is required for high performance computing (HPC) workloads in data centers. As a result, enabling data processing between machines and servers across long reach channels at high rates becomes mandatory. SoCs for HPC applications such as data center, networking and AI, must support high throughput and minimum latency with maximum… Keeping Latency to a Minimum with 400G/800G Ethernet IP
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Addressing Growing Security Challenges with JasperGold
Join Cadence® Training and Product Engineering Architect Joerg Mueller and Senior Application Engineer Tom Weiss for this free technical training webinar. As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality. Recent microarchitectural vulnerabilities like “Meltdown” and “Row Hammer” that expose… Addressing Growing Security Challenges with JasperGold
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Benefits of a Common Methodology for Emulation and Prototyping
Many design teams have used some form of hardware verification throughout their verification cycle for years now. Some engineering teams prefer to use emulation, some prefer to use prototyping, and some even use both. Why would engineering teams invest in both platforms? Join our experts to understand why you should consider bridging emulation and prototyping… Benefits of a Common Methodology for Emulation and Prototyping
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UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
Abstract: Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.… UVM for FPGAs (Part 4): IEEE 1800.2 UVM Updates
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Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
Overview As vehicles get more complex and connected, the attack surface increases. This presents increasing challenges for cybersecurity. This webinar introduces hardware based techniques for addressing security concerns, from legacy through to the future. What will you learn? The best use of threat modelling techniques Methods for staying one step ahead of malicious hackers in… Effectively Addressing the Challenge of Securing Connected and Autonomous Vehicles
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Iternational Test Conferece
International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how… Iternational Test Conferece
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CHIPS Alliance Workshop
CHIPS Alliance, the open source RTL hardware and software development tool organization, is gathering to share milestones, progress, updates and more.
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Methodics User Group
Join our monthly session with Methodics IPLM experts and other users for open discussion, Q&A, and product demos. Next Session: October 12 | 1:00 P.M. EST Each 30-minute session offers a new opportunity to: Learn/share best practices. Interact with and learn from other users. Have Q&A time with our product experts on usage and methodology.… Methodics User Group
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Firsst IEEE International Workshop on Silicon Lifecycle Management
AIM OF THE WORKSHOP With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable and secure operation of electronics in safety-critical, enterprise servers and cloud computing domains is still a major challenge. While traditionally design time and test time solutions were supposed to guarantee the… Firsst IEEE International Workshop on Silicon Lifecycle Management
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Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
Trends such as advanced driver assistance systems (ADAS) and autonomous driving (AD) make software the differentiating factor in the automotive industry. To keep pace with innovations and to shorten development cycles, testing of electronic control units (ECUs) must shift-left. The use of software-in-the-loop (SiL) simulations is a recognized and established approach to frontload test activities to earlier development phases. Recently, automotive… Entering a New Era with Linux-Based Automotive Software-in-the-Loop Test Tools
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SURGE Virtual Event North America 2021
Silvaco is pleased to invite you to join its annual SURGE users event, taking place virtually, on October 14, 2021. SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, share users’ experiences, and discover innovative techniques for advanced semiconductor design. This year we have a virtual event that includes cool prizes… SURGE Virtual Event North America 2021
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The most error prone FPGA corner cases
Presenter: Espen Tallaksen, CEO of EmLogic Thursday, October 14, 2021 Abstract: Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, - a cycle related corner case is for instance if you have an event counter where the number of counted… The most error prone FPGA corner cases
12 events found.