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Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs
Analog designers appreciate the importance of tight communication between layout and design teams, yet with geographically dispersed teams this can be a big challenge. Close collaboration between circuit designer and layout designer is essential for creating high-quality analog layouts. With this close connection and sharing feedback in a consistent way, analog designers can be sure… Enabling Effective Design & Layout Collaboration for Next Generation Analog and Mixed-Signal Designs
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The Evolution of Process TCAD in Semiconductor R&D and Manufacturing
Shela Aboud, Ph.D., Synopsys Today, nearly every aspect of an integrated circuit is designed using EDA software. Technology computer aided design (TCAD) tools are used for modeling front-end-of-line manufacturing, including the fabrication and electrical characterization of individual transistors. I will discuss how TCAD has evolved to keep up with technology evolution and how new drivers… The Evolution of Process TCAD in Semiconductor R&D and Manufacturing
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What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs
Testing an O-RAN Radio Unit (O-RU) SoC at full scale implies sending realistic traffic, in conformance with current specifications and at the right time on the right interfaces to simulate complex scenarios and cover as many corner cases as possible. It requires a robust debug methodology which can provide quick turn around and appropriate window… What’s Needed to Perform End-to-End Testing for 5G Open Radio Access Network SoCs
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3DIC 2021
North Carolina State University 1101 Garman St., Raleight, NC, United StatesIEEE International 3D System Integration Conference (3DIC) November 15-18, 2021 Raleigh, North Carolina, USA After a one-year hiatus, 3DIC will once again unite 2.5D/3D researchers and developers from all around the world. This year’s conference employs a hybrid format of in-person events and virtual events. Talks, panels, exhibits, papers, and discussions will foster a stimulating… 3DIC 2021
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Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Verifying changes to RTL and testbench code prior to releasing to the rest of your team is the best way to avoid committing bugs that cause massive, team-wide disruptions. This webinar takes you through example tool flows that, when used within a Continuous Integration (CI) system, can avoid or even eliminate those bugs and disruptions.… Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
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Accelerating Analog Layout
The growing demand for analog features on IoT devices means that analog designers are under constant pressure to complete more designs faster than ever. For most layout designers, analog layout remains a largely manual task, which creates real challenges for today’s pressured designers. Pulsic presents a new solution for analog layout automation. Animate Preview accelerates… Accelerating Analog Layout
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GSA – Asia Pacific Executive Forum
We invite you to join us at the 2021 Asia Pacific Executive Forum, happening virtually on Tuesday, November 16 at 9:00 AM HKT. In adapting to the challenges of COVID, the world has experienced dramatic changes that are redefining our daily lives. New capabilities empowered by AI, IoT, hyperscale computing and 5G are driving digital… GSA – Asia Pacific Executive Forum
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RISC-V Days Tokyo Autumn 2021
RISC-V Days Tokyo is Japan’s largest RISC-V event. We will hold live and online presentations, live exhibition booths, and press conferences. RISC-V Days Tokyo brings together excellent RISC-V-related technologies and products, as well as key persons and engineers, and provides business opportunities such as raising product awareness, realizing collaboration between companies, technology exchange, and information… RISC-V Days Tokyo Autumn 2021
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CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
Join us as Cadence experts describe common challenges and solutions in creating an efficient and accelerated flow that will meet technical requirements for accurately measuring the power, energy, and system performance while making essential design tradeoffs to meet your aggressive time-to-market schedule. In this CadenceTECHTALK, you will learn how to: Address the challenges of accelerating… CadenceTECHTALK: Power and Energy Optimization Using Tensilica IP
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Samsung SAFE Forum 2021
Join us for Samsung Foundry’s annual SAFE™ Forum. What will you take away from Samsung Foundry’s ecosystem event? Bump your SoC PPA knowledge with the latest information on: High speed interconnect IPs for HPC and Data Center applications and foundational IPs High bandwidth memory subsystems Key IP trends for automotive and mobile applications Foundational Analog… Samsung SAFE Forum 2021
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A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification
In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips through chip-to-chip gateways. The coherency protocol across interconnects… A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification
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Accelerate Semiconductor Technology Development and Innovation
Seminar Overview Join our online TCAD Seminar to learn about the application of Synopsys TCAD solutions to accelerate the research, development and optimization of semiconductor technologies. The seminar tracks cover all major semiconductor technologies, from advanced logic and memory to analog, power and optoelectronics. The solutions presented in this seminar are based on the industry-standard… Accelerate Semiconductor Technology Development and Innovation
12 events found.