-
-
Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
For the past 10+ years, semiconductor design has moved from a project-based "start again" mindset to a more modular, "IP-centric" approach. This has significantly reduced project cost and improved time-to-market by encouraging the outsourcing of niche areas of the design to specialists, enabling the use of foundry sourced IP (often for free) and emphasizing the… Managing SoC Subsystems and Other Hierarchy With Methodics IPLM
-
Xcelium ML for 5X Faster Regression Throughput
Overview Regressions time often becomes one of the biggest challenges to meet the tight project schedule with increasing complexity of the SoC designs and shorter time to market. Verification engineers apply a coverage-driven methodology and run a large number of constrained random tests with multiple seeds in massive regressions to meet their coverage goals. Thus,… Xcelium ML for 5X Faster Regression Throughput
-
Future Infrastructure—The Impact on the Semiconductor Industry (Northeast Forum)
The SEMI Northeast Forum will bring together industry leaders from along the semiconductor supply chain to discuss their vision of the impact the post-pandemic infrastructure will have on the semiconductor industry. The semiconductor industry has generally fared well during the recent pandemic, at least in part because it has supplied the technology that has allowed… Future Infrastructure—The Impact on the Semiconductor Industry (Northeast Forum)
-
-
40th Annual ICCAD
As ICCAD 2021's general chair, please let me announce that the main technical program of the 40th anniversary of ICCAD will take place purely virtual from November 1st (until November 4th) 2021, which is due to the ongoing pandemic situation. Thanks to the rapidly deployed vaccines and strict hygienic measures, ICCAD will be extended to offer… 40th Annual ICCAD
-
Intelligent Cross-Platform Workflows for RF PCB Integration
The last webinar in The Cadence® AWR® V16 for RF Design Excellence Webinar Seriesintroduces groundbreaking cross-platform workflows from AWR® software to Allegro® PCB Designer, which help to deliver up to a 50% reduction in turnaround time compared to competing solutions. RF IP integration within a larger mixed-signal PCB system is hampered by disjointed workflows between… Intelligent Cross-Platform Workflows for RF PCB Integration
-
Silvaco UseRs Global Event – Japan
開催日時：2021/11/02 13:00 SURGE (Silvaco UseRs Global Event)とは、シルバコが開催するワールドワイドのイベントです。 SURGEは、TCAD、EDA、IPの各分野において、新しい技術について議論し、ユーザの経験を共有し、先進的な半導体設計のための革新的な技術を発見するためのイベントです。 本年は、オンラインでの開催となります。 当日ご参加いただき、アンケートにご回答いただいたお客様の中から抽選で50名の方にAmazonギフト券1000円分(Eメールタイプ)を進呈させていただきます。 この機会に是非ともSURGE Japanにご登録ください。
-
Osmosis 2021 (OneSpin User Group)
What is Osmosis? Osmosis is the name for all users’ group events for customers and partners of OneSpin: A Siemens Business, provider of electronic design automation (EDA) tools for integrated circuit (IC) integrity verification. Though the Osmosis name is an acronym (OneSpin Meeting on Solutions, Innovation, & Strategy), it was chosen intentionally because of what the term osmosis represents: movement in two directions. In this… Osmosis 2021 (OneSpin User Group)
-
Understanding Random Stability in SystemVerilog and UVM
Webinar Overview: A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability. In this webinar, we explain: Random stability in SystemVerilog… Understanding Random Stability in SystemVerilog and UVM
-
28th Electronic Design Process Symposium
In 2021, the Electronic Design Process Symposium (EDPS) is in its 28th year, and it continues to serve as a leading forum for thought leaders of the design community from industry participants as well as academia. We invite industry leaders to discuss state-of-the-art improvements to the electronic design processes and CAD methodologies, emphasizing trends and… 28th Electronic Design Process Symposium
-
Constraint Random Verification with Python and Cocotb
Abstract: Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean writing test code can’t be enjoyable and productive! Cocotb, an approach to use Python as verification language, is bringing the joy back to verification. It allows developers to start with small, directed testbenches,… Constraint Random Verification with Python and Cocotb
-
Wafers to Wall Street—The Road Forward: Look at Technology and the Emerging Trends Affecting Growth
Biamp Systems 9300 SW Gemini Dr., Beaverton, OR, United StatesA Look at Technology and the Emerging Trends Affecting Growth Over the past year, we have seen major companies continue to make significant, impactful investments in their operations as they look to meet market demand. Join Industry and Wall Street Experts for an in-person forum to discuss the various facets driving current growth, semiconductors’ future… Wafers to Wall Street—The Road Forward: Look at Technology and the Emerging Trends Affecting Growth
-
Boost LPDDR5 Verification from IP to System Level
Overview Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall… Boost LPDDR5 Verification from IP to System Level
12 events found.