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Boost LPDDR5 Verification from IP to System Level

November 9 @ 10:00 am - 11:00 am PST

Cadence November 9

Overview

Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. The specification complexity is increasing to meet higher bandwidth, better performance and extended latencies for multiple use cases. Ensuring that JEDEC low-power double data rate 5 (LPDDR5) specification and overall System on Chip (SoC) requirements are fully met makes verification extremely challenging.

Join us to learn about LPDDR5 verification challenges from IP-level to system-level and demonstrate how these challenges can be significantly mitigated using advanced verification methodologies and tools.

This webinar will cover the following topics:

· Verification challenges of LPDDR5 designs

· IP-level verification for specification’s compliancy

· System-level verification in simulation and emulation

Date

Tuesday, November 9, 2021

Time

EMEA and APJ Sessions: 09:00 BST / 10:00 CEST / 11:00 EEST and IDT / 13:30 IST/ 16:00 CST/17:00 JST

North America Session: 10:00 PDT / 13:00 EDT

Details

Date:
November 9
Time:
10:00 am - 11:00 am PST
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Event Tags:
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Event Site

Organizer

Cadence
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