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Tackling Advanced Analog FinFET Back-End Design Challenges
The layout implementation of analog circuits in advanced FinFET technologies is becoming increasingly complex and challenging, with many new design rules to consider and multi-patterning, density rules, matching, and EM-IR concerns. These challenges can translate to longer layout turnaround times and reduced productivity. Join this CadenceTECHTALK to learn about silicon-proven technologies that improve layout engineering… Tackling Advanced Analog FinFET Back-End Design Challenges
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FPGA Design/Verification: Randomization
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design, and as a result their products have significantly more undetected bugs. Randomization can be used in many ways, but it… FPGA Design/Verification: Randomization
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Phil Kaufman Award Ceremony & Banquet
The GlassHouse 2 S Market Street, San Jose, CA, United StatesThe Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. Time 6:30… Phil Kaufman Award Ceremony & Banquet
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Advantest VOICE 2022
OMNI Scottsdale Resort Scottsdale, AZ, United StatesVOICE Registration is sold out and the event is at full capacity. We apologize for any inconvenience. VOICE is a developer conference, created by test engineers for test engineers. Each year, the VOICE Developer Conference unites semiconductor test professionals representing the world's leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly… Advantest VOICE 2022
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Embedded Vision Summit
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe premier event for practical, deployable computer vision and visual AI, for product creators who want to bring visual intelligence to products. The Summit attracts a global audience of technology professionals from companies developing computer vision and edge AI-enabled products including embedded systems, cloud solutions and mobile applications. Why attend? It's a First-Rate Program with… Embedded Vision Summit
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Writing C/C++ Models for Efficient Datapath Validation Using VC Formal DPV
Wednesday, May 18, 2022 | 10:00 - 11:00 a.m. Pacific AI, Graphics, CPU, and many modern designs have arithmetic intensive blocks that are hard to verify with traditional techniques. Synopsys VC Formal DPV (Datapath Validation) has been the industry's golden standard to get closure on datapath verification. In this Synopsys webinar, we will discuss why… Writing C/C++ Models for Efficient Datapath Validation Using VC Formal DPV
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Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
The Peripheral Component Interconnect Express (PCIe®) high-speed interface has become the standard for computer expansion cards due to its high bandwidth combined with manageable component costs. However, the latest PCIe 6.0 release raises new challenges for design engineers, as the popular interface standard moves to pulse-amplitude modulation-4 (PAM-4) signaling for the first time. This webinar… Conquer SI/PI Challenges and Reduce Time to Signoff for PCIe 6.0
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FPGA Design/Verification: Code, Functional and Specification Coverage
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench. Unfortunately, not many designers are applying… FPGA Design/Verification: Code, Functional and Specification Coverage
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IEEE ISPSD 2022
Marriott Pinnacle Downtown Hotel Vancouver, BC, CanadaThe IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) is the premier forum for technical discussions in all areas of power semiconductor devices and power integrated circuits. Topics include, but not limited to, device physics, modelling, design, fabrication, materials, packaging and integration, device reliability, and device/circuit interactions. The conference venue rotates annually through… IEEE ISPSD 2022
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European Test Symposium 2022
Casa Convalescencia Barcelona, SpainThe IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuits and system testing, reliability, security and validation. ETS’22 will be held in Casa Convalescència, located in the historical modernist site Hospital de la Santa… European Test Symposium 2022
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A Faster Path to Analog Layout
Pulsic Webinars are back! Fast forward to the future of analog layout with this Mark Waller's webinar. In this webinar you will learn how to shrink your design time by 60% with Animate Preview. You are just one (free) click away from the future of analog design:
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Automotive Cyber-Security: Off-board and On-board, standards and technologies
This webinar will help you understand: • The different standards that exist and why is compliance so important? • How to protect against tampering attacks? • What is lifecycle security and how can it benefit the automotive industry? • Why is it important to protect the whole lifecycle of a device?
12 events found.